%C258
C258 Architecture
Mnemonic: C258                Mnemonic: DIP/PLCC
Pin Count: 28             Total Product Terms:  2048
Extensions: D DQ AP AR CKMUX OEMUX
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
CYPRESS                       CY7C258
_____________________________________________________________
Clock Pin(s): 26              Common OE(s): 28
VCC(s): 7  21                 GND(s): 8  20  22
Input Only: 1  2  3  4  5  6  9  10  11  12  13  14  27
Output Only: 18  19  23  24  25
Input/Output: 15  16  17
%%
%C259
C259 Architecture
Mnemonic: C259                Mnemonic: PLCC
Pin Count: 44             Total Product Terms:  2048
Extensions: D DQ AP AR CKMUX OEMUX
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
CYPRESS                       CY7C259
_____________________________________________________________
Clock Pin(s): 44              Common OE(s): 4
VCC(s): 8  11  20  22  30     GND(s): 1  12  14  28  29  36
        35                            43
Input Only: 2  3  4  5  6  7  9  10  13  15  16  17  18  19
Output Only: 38  39  40  41  42
Input/Output: 21  23  24  25  26  27  31  32  33  34  37
%%
%C330
C330 Architecture
Mnemonic: C330                Mnemonic: DIP/PLCC
Pin Count: 28             Total Product Terms:  258
Extensions: D DQ IOD OE SR SP IOCKMUX CKMUX OEMUX IMUX
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
CYPRESS                       CY7C330
_____________________________________________________________
Clock Pin(s): 1  2  3         Common OE(s): 14
VCC(s): 22                    GND(s): 8  21
Input Only: 2  3  4  5  6  7  9  10  11  12  13  14
Output Only:
Input/Output: 15  16  17  18  19  20  23  24  25  26  27  28
Internal Nodes: 29  30  31  32
%%
%C331
C331 Architecture
Mnemonic: C331                Mnemonic: DIP/PLCC
Pin Count: 28             Total Product Terms:  216
Extensions: D DQ AR AP IMUX OE CK OEMUX IOD IOAR IOAP IOCK
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
CYPRESS                       CY7C331
_____________________________________________________________
Clock Pin(s): 1  2  3         Common OE(s): 14
VCC(s): 22                    GND(s): 8  21
Input Only: 2  3  4  5  6  7  9  10  11  12  13  14
Output Only:
Input/Output: 15  16  17  18  19  20  23  24  25  26  27  28
%%
%C332
C332 Architecture
Mnemonic: C332                Mnemonic: DIP/PLCC
Pin Count: 28             Total Product Terms:  194
Extensions: DQ LQ LEMUX OE IOCKMUX CKMUX OEMUX IO IOD IOL
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
CYPRESS                       CY7C332
_____________________________________________________________
Clock Pin(s): 1  2  3         Common OE(s): 14
VCC(s): 22                    GND(s): 8  21
Input Only: 2  3  4  5  6  7  9  10  11  12  13  14
Output Only:
Input/Output: 15  16  17  18  19  20  23  24  25  26  27  28
%%
%C335
C335 Architecture
Mnemonic: C335                Mnemonic: DIP/PLCC
Pin Count: 28             Total Product Terms:  258
Extensions: D DQ IOD OE SR SP IOCKMUX CKMUX OEMUX IMUX
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
CYPRESS                       CY7C335
_____________________________________________________________
Clock Pin(s): 1  2  3         Common OE(s): 14
VCC(s): 22                    GND(s): 8  21
Input Only: 2  3  4  5  6  7  9  10  11  12  13  14
Output Only:
Input/Output: 15  16  17  18  19  20  23  24  25  26  27  28
Internal Nodes:  29  30  31  32
%%
%C336
C336 Architecture
Mnemonic: C336                Mnemonic: DIP/PLCC
Pin Count: 28             Total Product Terms:  16
Extensions: OE DQ
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
CYPRESS                       CY7BC336
_____________________________________________________________
Clock Pin(s): 1  2  3         Common OE(s): 14
VCC(s): 22                    GND(s): 8  21
Input Only: 2  3  4  5  6  7  9  10  11  12  13  14
Output Only:
Input/Output: 15  16  17  18  19  20  23  24  25  26  27  28
%%
%C337
C337 Architecture
Mnemonic: C337                Mnemonic: DIP/PLCC
Pin Count: 28             Total Product Terms:  32
Extensions: DQ
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
CYPRESS                       CY7BC337
_____________________________________________________________
Clock Pin(s): 1  2  3         Common OE(s): 14
VCC(s): 22                    GND(s): 8  21
Input Only: 2  3  4  5  6  7  9  10  11  12  13  14
Output Only:
Input/Output: 15  16  17  18  19  20  23  24  25  26  27  28
%%
%C338
C338 Architecture
Mnemonic: C338                Mnemonic: DIP/PLCC
Pin Count: 28             Total Product Terms:  16
Extensions: OE L
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
CYPRESS                       CY7BC338
_____________________________________________________________
Clock Pin(s): 1  2  3         Common OE(s): 14
VCC(s): 22                    GND(s): 8  21
Input Only: 2  3  4  5  6  7  9  10  11  12  13  14
Output Only:
Input/Output: 15  16  17  18  19  20  23  24  25  26  27  28
%%
%C339
C339 Architecture
Mnemonic: C339                Mnemonic: DIP/PLCC
Pin Count: 28             Total Product Terms:  32
Extensions: L
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
CYPRESS                       CY7BC339
_____________________________________________________________
Clock Pin(s): 1  2  3         Common OE(s): 14
VCC(s): 22                    GND(s): 8  21
Input Only: 2  3  4  5  6  7  9  10  11  12  13  14
Output Only:
Input/Output: 15  16  17  18  19  20  23  24  25  26  27  28
%%
%C371
C371 Architecture
Mnemonic: C371                Mnemonic: PLCC
Pin Count: 44             Total Product Terms: 140
Extensions: D T L DQ LQ AP AR CK CKMUX LE LEMUX OE OEMUX INT
            IO IOD IOL IOCK
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
CYPRESS                       CY7C371
_____________________________________________________________
Clock Pin(s): 13  35          Common OE(s):
VCC(s): 22  44                GND(s): 1  12  23  34
Input Only: 10  11  13  32  33  35
Output Only:
Input/Output: 2  3  4  5  6  7  8  9  14  15  16  17  18  19
              20  21  24  25  26  27  28  29  30  31  36  37
              38  39  40  41  42  43
%%
%C372
C372 Architecture
Mnemonic: C372                Mnemonic: PLCC
Pin Count: 44             Total Product Terms: 140
Extensions: D T L DQ LQ AP AR CK CKMUX LE LEMUX OE OEMUX INT
            IO IOD IOL IOCK
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
CYPRESS                       CY7C372
_____________________________________________________________
Clock Pin(s): 13  35          Common OE(s):
VCC(s): 22  44                GND(s): 1  12  23  34
Input Only: 10  11  13  32  33  35
Output Only:
Input/Output: 2  3  4  5  6  7  8  9  14  15  16  17  18  19
              20  21  24  25  26  27  28  29  30  31  36  37
              38  39  40  41  42  43
%
%C373
C373 Architecture
Mnemonic: C373             Mnemonic: PLCC
Pin Count: 84             Total Product Terms: 720
Extensions: D T L DQ LQ AP AR CK CKMUX LE LEMUX OE OEMUX INT
            IO IOD IOL IOCK
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
CYPRESS                        CY7C373
_____________________________________________________________
Clock Pin(s): 20  23  62  65 Common OE(s):
VCC(s): 2  21  42  63  74 84 GND(s):1  11 22  32  43  53  64
Input Only: 20  23  41  62  65  83
Output Only:
Input/Output: 3  4  5  6  7  8  9  10 12  13  14  15  16  17
              18  19  24  25  26  27  28  29  30  31  33  34
              35  36  37  38  39  40  45  46  47  48  49  50
              51  52  54  55  56  57  58  59  60  61  66  67
              68  69  70  71  72  73  75  76  77  78  79  80
              81  82
%%
%C373t
C373t Architecture
Mnemonic: C373t                Mnemonic: TQFP
Pin Count: 100             Total Product Terms: 720
Extensions: D T L DQ LQ AP AR CK CKMUX LE LEMUX OE OEMUX INT
            IO IOD IOL IOCK
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
CYPRESS                        CY7C373
_____________________________________________________________
Clock Pin(s):                Common OE(s):
VCC(s):                      GND(s):
Input Only:
Output Only:
Input/Output:

%%
%C374
C374 Architecture
Mnemonic: C374                Mnemonic: PLCC
Pin Count: 84             Total Product Terms: 720
Extensions: D T L DQ LQ AP AR CK CKMUX LE LEMUX OE OEMUX INT
            IO IOD IOL IOCK
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
CYPRESS                        CY7C374
_____________________________________________________________
Clock Pin(s): 20  23  62  65 Common OE(s):
VCC(s): 2  21  42  63  74 84 GND(s):1  11 22  32  43  53  64
Input Only: 20  23  41  62  65  83
Output Only:
Input/Output: 3  4  5  6  7  8  9  10 12  13  14  15  16  17
              18  19  24  25  26  27  28  29  30  31  33  34
              35  36  37  38  39  40  45  46  47  48  49  50
              51  52  54  55  56  57  58  59  60  61  66  67
              68  69  70  71  72  73  75  76  77  78  79  80
              81  82
%%
%C374t
C374t Architecture
Mnemonic: C374t               Mnemonic: TQFP
Pin Count: 100            Total Product Terms: 720
Extensions: D T L DQ LQ AP AR CK CKMUX LE LEMUX OE OEMUX INT
            IO IOD IOL IOCK
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
CYPRESS                        CY7C374
_____________________________________________________________
Clock Pin(s):                Common OE(s):
VCC(s):                      GND(s):
Input Only:
Output Only:
Input/Output:

%%
%C375
C375 Architecture
Mnemonic: C375                Mnemonic: TQFP
Pin Count: 160            Total Product Terms: 1440
Extensions: D T L DQ LQ AP AR CK CKMUX LE LEMUX OE OEMUX INT
            IO IOD IOL IOCK
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
CYPRESS                        CY7C375
_____________________________________________________________
Clock Pin(s):                Common OE(s):
VCC(s):                      GND(s):
Input Only:
Output Only:
Input/Output:

%%
%EP1200
EP1200 Architecture
Mnemonic: EP1200              Mnemonic: DIP
Pin Count: 40             Total Product Terms:  236
Extensions: LQ D OE AR IOL DFB CKMUX LEMUX
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
ALTERA                        EP1200
ALTERA                        EP1210
INTEL                         5C121
_____________________________________________________________
Clock Pin(s): 1               Common OE(s):
VCC(s): 39  40                GND(s): 20
Input Only: 2  3  4  5  6  7  33  34  35  36  37  38
Output Only:
Input/Output: 8  9  10  11  12  13  14  15  16  17  18  19
              21  22  23  24  25  26  27  28  29  30  31  32
_____________________________________________________________
Device Notes:
1.  Turbo bit:     15145
%%
%EP1800
EP1800 Architecture
Mnemonic: EP1800              Mnemonic: PLCC
Pin Count: 68             Total Product Terms:  480
Extensions: OE D T AR CK IO DFB TFB INT
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
ALTERA                        EP1800
ALTERA                        EP1810
ALTERA                        EP1830
INTEL                         5C180
TI                            EP1810
_____________________________________________________________
Clock Pin(s): 17  19  51  53  Common OE(s):
VCC(s): 18  52                GND(s): 1  35
Input Only: 14  15  16  20  21  22  48  49  54  55  56
Output Only:
Input/Output: 2  3  4  5  6  7  8  9  10  11  12  13  23
              24  25  26  27  28  29  30  31  32  33  34
              36  37  38  39  40  41  42  43  44  45  46
              47  50  57  58  59  60  61  62  63  64  65
              66  67  68
_____________________________________________________________
Device Notes:
1.  Miser bits:    42480-42487
    Turbo bits:    42488-42489
%%
%EP300
EP300 Architecture
Mnemonic: EP300               Mnemonic: DIP
Pin Count: 20             Total Product Terms:   74
Extensions: OE D AR SP INT DFB IO
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
ALTERA                        EP300
ALTERA                        EP310
INTEL                         5C031
_____________________________________________________________
Clock Pin(s): 1               Common OE(s):
VCC(s): 20                    GND(s): 10
Input Only: 2  3  4  5  6  7  8  9  11
Output Only:
Input/Output: 12  13  14  15  16  17  18  19
_____________________________________________________________
Device Notes:
1.   The registered, internal combinatorial and I/O feedback
     paths can be selected by using the .DFB, .INT and .IO
     extensions respectively. If the feedback type is the
     same as the output (registered feedback for registered
     output), a feedback extension is not required.
%%
%EP312
EP312 Architecture
Mnemonic: EP312               Mnemonic: DIP
Pin Count: 24             Total Product Terms:  200
Extensions: D T DQ LQ CK LE AR AP INT OE CKMUX IO LEMUX
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
ALTERA                        EP512
INTEL                         5AC312
_____________________________________________________________
Clock Pin(s): 1               Common OE(s):
VCC(s): 24                    GND(s): 12
Latch Enable: 13
Input Only: 1  3  4  5  6  7  8  9  10  13
Output Only:
Input/Output: 2  11  14  15  16  17  18  19  20  21  22  23
_____________________________________________________________
Device Notes:
1.  Turbo bit:     13712
%%
%EP312lcc
EP312lcc Architecture
Mnemonic: EP312               Mnemonic: PLCC
Pin Count: 24             Total Product Terms:  200
Extensions: D T DQ LQ CK LE AR AP INT OE CKMUX IO LEMUX
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
ALTERA                        EP512
INTEL                         5AC312
_____________________________________________________________
Clock Pin(s): 2               Common OE(s):
VCC(s): 1  28                 GND(s): 14  15
Latch Enable: 16
N/C:  11  19
Input Only: 2  4  5  6  7  8  9  10  16
Output Only:
Input/Output: 3  13  17  18  20  21  22  23  24  25  26  27
_____________________________________________________________
Device Notes:
1.  Turbo bit:     13712
%%
%EP320
EP320 Architecture
Mnemonic: EP320               Mnemonic: DIP
Pin Count: 20             Total Product Terms:   72
Extensions: OE D
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
ALTERA                        EP320
ALTERA                        EP330
INTEL                         5C032
INTEL                         85C220
TI                            EP330
_____________________________________________________________
Clock Pin(s): 1               Common OE(s):
VCC(s): 20                    GND(s): 10
Input Only: 1  2  3  4  5  6  7  8  9  11
Output Only:
Input/Output: 12  13  14  15  16  17  18  19
_____________________________________________________________
Device Notes:
1.  Miser bits:    2912-2913
    Turbo bits:    2914-2915
%%
%EP324
EP324 Architecture
Mnemonic: EP324               Mnemonic: DIP
Pin Count: 40             Total Product Terms:  394
Extensions: D T DQ LQ CK LE AR AP INT OE CKMUX IO LEMUX
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
INTEL                         5AC324
_____________________________________________________________
Clock Pin(s): 1               Common OE(s):
VCC(s): 13  33                GND(s): 8  28
Latch Enable: 21
Input Only: 1  2  3  18  19  20  21  22  23  38  39  40
Output Only:
Input/Output: 4  5  6  7  9  10  11  12  14  15  16  17  24
               25  26  27  29  30  31  32  34  35  36  37
_____________________________________________________________
Device Notes:
1.  Turbo bit:     47492
%%
%EP324lcc
EP324lcc Architecture
Mnemonic: EP324lcc            Mnemonic: PLCC
Pin Count: 40             Total Product Terms:  394
Extensions: D T DQ LQ CK LE AR AP INT OE CKMUX IO LEMUX
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
INTEL                         5AC324
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Latch Enable:
Input Only:
Output Only:
Input/Output:
_____________________________________________________________
Device Notes:
1.  Turbo bit:     47492
%%
%EP600
EP600 Architecture
Mnemonic: EP600               Mnemonic: DIP
Pin Count: 24             Total Product Terms:  160
Extensions: OE D T AR CK IO DFB TFB
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
ALTERA                        EP600
ALTERA                        EP610
ALTERA                        EP610T
ALTERA                        EP630
AMD/MMI                       PALCE610
CYPRESS                       CY7B326
INTEL                         5C060
INTEL                         85C060
TI                            EP610
TI                            EP630
_____________________________________________________________
Clock Pin(s): 1  13           Common OE(s):
VCC(s): 24                    GND(s): 12
Input Only: 2  11  14  23
Output Only:
Input/Output: 3  4  5  6  7  8  9  10  15  16  17  18  19
              20  21  22
_____________________________________________________________
Device Notes:
1.  Support for registered mode of the macrocell consists
    only of D-type and T-type flip-flops. J-K and S-R
    flip-flops are not supported because they don't
    physically exist in the device. They must be emulated
    with exclusive-or equations.
2.  The D-type registered, T-type registered, and I/O
    feedback paths can be selected by using the .DFB, .TFB
    and .IO extensions respectively. If the feedback type is
    the same as the output (D-type registered feedback for
    D-type registered output), then feedback extension is
    not required.
3.  Turbo bits:    6480-6481
     EP900/910 Turbo bits:    17400-17401
%%
%EP600lcc
EP600lcc Architecture
Mnemonic: EP600lcc        Mnemonic: PLCC
Pin Count: 28             Total Product Terms:  160
Extensions: OE D T AR CK IO DFB TFB
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
ALTERA                        EP600
ALTERA                        EP610
ALTERA                        EP610T
ALTERA                        EP630
AMD/MMI                       PALCE610
CYPRESS                       CY7B326
INTEL                         5C060
INTEL                         85C060
TI                            EP610
TI                            EP630
_____________________________________________________________
Clock Pin(s): 2  16           Common OE(s):
VCC(s): 1  28                 GND(s): 14  15
Input Only: 2  3  13  16  17  27
Output Only:
Input/Output: 4  5  6  7  8  9  10  12  18  20  21  22  23
              24  25  26
_____________________________________________________________
Device Notes:
1.  Support for registered mode of the macrocell consists
    only of D-type and T-type flip-flops. J-K and S-R
    flip-flops are not supported because they don't
    physically exist in the device. They must be emulated
    with exclusive-or equations.
2.  The D-type registered, T-type registered, and I/O
    feedback paths can be selected by using the .DFB, .TFB
    and .IO extensions respectively. If the feedback type is
    the same as the output (D-type registered feedback for
    D-type registered output), then feedback extension is
    not required.
3.  Turbo bits:    6480-6481
     EP900/910 Turbo bits:    17400-17401
%%
%EP900
EP900 Architecture
Mnemonic: EP900               Mnemonic: DIP
Pin Count: 40             Total Product Terms:  240
Extensions: OE D T AR CK IO DFB TFB
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
ALTERA                        EP900
ALTERA                        EP910
ALTERA                        EP910A
ALTERA                        EP910T
INTEL                         5C090
INTEL                         85C090
TI                            EP910
_____________________________________________________________
Clock Pin(s): 1  21           Common OE(s):
VCC(s): 40                    GND(s): 20
Input Only: 2  3  4  17  18  19  22  23  24  37  38  39
Output Only:
Input/Output: 5  6  7  8  9  10  11  12  13  14  15  16  25
               26  27  28  29  30  31  32  33  34  35  36
_____________________________________________________________
Device Notes:
1.  Support for registered mode of the macrocell consists
    only of D-type and T-type flip-flops. J-K and S-R
    flip-flops are not supported because they don't
    physically exist in the device. They must be emulated
    with exclusive-or equations.
2.  The D-type registered, T-type registered, and I/O
    feedback paths can be selected by using the .DFB, .TFB
    and .IO extensions respectively. If the feedback type is
    the same as the output (D-type registered feedback for
    D-type registered output), then feedback extension is
    not required.
3.  Turbo bits:    17400-17401
%%
%EP900lcc
EP900lcc Architecture
Mnemonic: EP900lcc        Mnemonic: PLCC
Pin Count: 44             Total Product Terms:  240
Extensions: OE D T AR CK IO DFB TFB
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
ALTERA                        EP900
ALTERA                        EP910
ALTERA                        EP910A
ALTERA                        EP910T
INTEL                         5C090
INTEL                         85C090
TI                            EP910
_____________________________________________________________
Clock Pin(s): 2  24           Common OE(s):
VCC(s): 1  44                 GND(s): 22  23
N/C:  17  29
Input Only: 3  4  5  19  20  21  25  26  27  41  42  43
Output Only:
Input/Output: 6  7  8  9  10  11  12  13  14  15  16  18  28
               29  30  31  32  33  34  35  36  37  38  40
_____________________________________________________________
Device Notes:
1.  Support for registered mode of the macrocell consists
    only of D-type and T-type flip-flops. J-K and S-R
    flip-flops are not supported because they don't
    physically exist in the device. They must be emulated
    with exclusive-or equations.
2.  The D-type registered, T-type registered, and I/O
    feedback paths can be selected by using the .DFB, .TFB
    and .IO extensions respectively. If the feedback type is
    the same as the output (D-type registered feedback for
    D-type registered output), then feedback extension is
    not required.
3.  Turbo bits:    17400-17401
%%
%F100
F100 Architecture
Mnemonic: F100                Mnemonic: DIP
Pin Count: 28             Total Product Terms:   48
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
FAIRCHILD                     93Z458
FAIRCHILD                     93Z459
PHILIPS                       82S100
PHILIPS                       82S101
PHILIPS                       PLS100
PHILIPS                       PLS101
_____________________________________________________________
Clock Pin(s):                 Common OE(s): 19
VCC(s): 28                    GND(s): 14
Input Only: 2  3  4  5  6  7  8  9  20  21  22  23  24  25
            26  27

Output Only: 10  11  12  13  15  16  17  18
Input/Output:
Unused: 1
%%
%F103
F103 Architecture
Mnemonic: F103                Mnemonic: DIP
Pin Count: 28             Total Product Terms:    9
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
PHILIPS                       82S103
PHILIPS                       PLS103
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
%%
%F105
F105 Architecture
Mnemonic: F105                Mnemonic: DIP
Pin Count: 28             Total Product Terms:   48
Extensions: S R CA OE AP
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       PLS105
PHILIPS                       82S105
PHILIPS                       82S105A
PHILIPS                       PLS105
PHILIPS                       PLS105A
PHILIPS                       PLUS105
TI                            N82S105A
TI                            TIB82S105A/B
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
%%
%F1500
F1500 Architecture
Mnemonic: F1500               Mnemonic: PLCC
Pin Count: 44             Total Product Terms:   320
Extensions: D T S R OE OEMUX CK CKMUX AR DQ LQ IO IOD IOL
            IOCK IOAR
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
ATMEL                         ATF1500A/AL
_____________________________________________________________
Clock Pin(s):                Common OE(s): 2  44
VCC(s): 3  15  23  35        GND(s): 10  22  30  42
GCLR: 1
Input Only:  1  2  43  44
Output Only:
Input/Output:  4  5  6  7  8  9  11  12  13  14  16  17  18
               19  20  21  24  25  26  27  28  29  31  32  33
               34  36  37  38  39  40  41
%%
%F1500T
F1500T Architecture
Mnemonic: F1500T              Mnemonic: TQPF
Pin Count: 44             Total Product Terms:   320
Extensions: D T S R OE OEMUX CK CKMUX AR DQ LQ IO IOD IOL
            IOCK IOAR
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
ATMEL                         ATF1500A/AL
_____________________________________________________________
Clock Pin(s): 37             Common OE(s): 38  40
VCC(s): 9  17  29  41        GND(s): 4  16  24  36
GCLR: 39
Input Only:  37  38  39  40
Output Only:
Input/Output:  1  2  3  5  6  7  8  10  11  12  13  14  15  18
               19  20  21  22  23  25  26  27  28  30  31  32
               33  34  35  42  43  44
%%
%F1508ispplcc68
F1508ispplcc68 Architecture
Mnemonic: F1508ispplcc68      Mnemonic: PLCC
Pin Count: 68             Total Product Terms:   320
Extensions: D T S R OE OEMUX CK CKMUX AR DQ LQ IO IOD IOL
            IOCK IOAR
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
ATMEL                         ATF1508
_____________________________________________________________
Clock Pin(s):  1  65  67      Common OE(s):  68
VCC(s):  3  11  21  31  35  43  53  63
GND(s):  6  16  26  34  38  48  58  66
GCLR:  1
Input Only:  1  2  67  68
Output Only:
Input/Output: 4  5  7  8  9  10  12  13  14  15  17  18  19
              20  22  23  24  25  27  28  29  30  32  33  36
              37  39  40  41  42  44  45  46  47  48  50  51
              52  54  55  56  57  59  60  61  62  64  65
ISP:  10  36  12  19  50  57
%%
%F1508ispplcc84
F1508ispplcc84 Architecture
Mnemonic: F1508ispplcc84      Mnemonic: PLCC
Pin Count: 84             Total Product Terms:   320
Extensions: D T S R OE OEMUX CK CKMUX AR DQ LQ IO IOD IOL
            IOCK IOAR
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
ATMEL                         ATF1508
_____________________________________________________________
Clock Pin(s):  2  81  83      Common OE(s): 84
VCC(s): 3  13  26  38  43  53  66  78
GND(s): 7  19  32  42  47  59  72  82
GCLR:  1
Input Only: 1  2  83  84
Output Only:
Input/Output: 4  5  6  8  9  10  11  12  14  15  16  17  18
              20  21  22  23  24  25  27  28  29  30  31  33
              34  35  36  37  39  40  41  44  45  46  48  49
              50  51  52  54  55  56  57  58  60  61  62  63
              64  65  67  68  69  70  71  73  74  75  76  77
              79  80  81
ISP:  12  45  14  23  62  71
%%
%F1508ispqfp100
F1508ispqfp100 Architecture
Mnemonic: F1508ispqfp100       Mnemonic: PQFP
Pin Count: 100            Total Product Terms:   320
Extensions: D T S R OE OEMUX CK CKMUX AR DQ LQ IO IOD IOL
            IOCK IOAR
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
ATMEL                         ATF1508
_____________________________________________________________
Clock Pin(s):  87  89  92     Common OE(s): 90
VCC(s):  5  20  36  41  53  68  84  93
GND(s):  13  28  40  45  61  76  88  97
Input Only:  89  90  91  92
Output Only:
Input/Output: 1  2  3  4  6  7  8  9  10  11  12  14  15  16
              17  18  19  20  21  22  23  24  25  27  28  29
              30  31  32  33  34  35  37  38  39  42  43  44
              46  48  49  50  51  52  54  55  56  57  58  60
              62  63  64  65  66  67  69  70  71  72  73  74
              75  77  78  79  80  81  82  83  85  86  87  94
              95  96  98  99  100
ISP:  3  43  6  17  64  75
%%
%F1508plcc68
F1508plcc68 Architecture
Mnemonic: F1508plcc68         Mnemonic: PLCC
Pin Count: 68             Total Product Terms:   320
Extensions: D T S R OE OEMUX CK CKMUX AR DQ LQ IO IOD IOL
            IOCK IOAR
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
ATMEL                         ATF1508
_____________________________________________________________
Clock Pin(s):  1  65  67      Common OE(s):  68
VCC(s):  3  11  21  31  35  43  53  63
GND(s):  6  16  26  34  38  48  58  66
GCLR:  1
Input Only:  1  2  67  68
Output Only:
Input/Output: 4  5  7  8  9  10  12  13  14  15  17  18  19
              20  22  23  24  25  27  28  29  30  32  33  36
              37  39  40  41  42  44  45  46  47  48  50  51
              52  54  55  56  57  59  60  61  62  64  65
%%
%F1508plcc84
F1508plcc84 Architecture
Mnemonic: F1508plcc84         Mnemonic: PLCC
Pin Count: 84             Total Product Terms:   320
Extensions: D T S R OE OEMUX CK CKMUX AR DQ LQ IO IOD IOL
            IOCK IOAR
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
ATMEL                         ATF1508
_____________________________________________________________
Clock Pin(s):  2  81  83      Common OE(s): 84
VCC(s): 3  13  26  38  43  53  66  78
GND(s): 7  19  32  42  47  59  72  82
GCLR:  1
Input Only: 1  2  83  84
Output Only:
Input/Output: 4  5  6  8  9  10  11  12  14  15  16  17  18
              20  21  22  23  24  25  27  28  29  30  31  33
              34  35  36  37  39  40  41  44  45  46  48  49
              50  51  52  54  55  56  57  58  60  61  62  63
              64  65  67  68  69  70  71  73  74  75  76  77
              79  80  81
%%
%F1508qfp100
F1508qfp100 Architecture
Mnemonic: F1508qfp100          Mnemonic: PQFP
Pin Count: 100            Total Product Terms:   320
Extensions: D T S R OE OEMUX CK CKMUX AR DQ LQ IO IOD IOL
            IOCK IOAR
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
ATMEL                         ATF1508
_____________________________________________________________
Clock Pin(s):  87  89  92     Common OE(s): 90
VCC(s):  5  20  36  41  53  68  84  93
GND(s):  13  28  40  45  61  76  88  97
Input Only:  89  90  91  92
Output Only:
Input/Output: 1  2  3  4  6  7  8  9  10  11  12  14  15  16
              17  18  19  20  21  22  23  24  25  27  28  29
              30  31  32  33  34  35  37  38  39  42  43  44
              46  48  49  50  51  52  54  55  56  57  58  60
              62  63  64  65  66  67  69  70  71  72  73  74
              75  77  78  79  80  81  82  83  85  86  87  94
              95  96  98  99  100
%%
%F151
F151 Architecture
Mnemonic: F151                Mnemonic: DIP
Pin Count: 20             Total Product Terms:   15
Extensions: OE
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
PHILIPS                       82S151
PHILIPS                       PLS151
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
%%
%F153
F153 Architecture
Mnemonic: F153                Mnemonic: DIP
Pin Count: 20             Total Product Terms:   42
Extensions: OE
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
GOULD                         PEEL153
HARRIS                        HPL77153
HARRIS                        HPL82S153
ICT                           PEEL153
PHILIPS                       82S153
PHILIPS                       82S153A
PHILIPS                       PLC153
PHILIPS                       PLHS153
PHILIPS                       PLS152
PHILIPS                       PLS153
PHILIPS                       PLS153A
PHILIPS                       PLUS153B/D
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s): 20                    GND(s): 10
Input Only: 1  2  3  4  5  6  7  8
Output Only:
Input/Output: 9  11  12  13  14  15  16  17  18  19
%%
%F155
F155 Architecture
Mnemonic: F155                Mnemonic: DIP
Pin Count: 20             Total Product Terms:   43
Extensions: OE D AR AP J K CA
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
PHILIPS                       82S155
PHILIPS                       PLS155
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
_____________________________________________________________
Device Notes:
1.   Registers may be used as either D-type or JK-type, but
     not both (no dynamic conversion).
2.   The output enable buffer for all registers is always
     controlled by pin 11.
3.   The load control term (for loading registers from the
     output pins) is not supported.
4.   The product term that drives the register control
     buffer is fixed and may not be accessed to drive the
     complement array.
%%
%F157
F157 Architecture
Mnemonic: F157                Mnemonic: DIP
Pin Count: 20             Total Product Terms:   43
Extensions: OE D AR AP J K CA
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
PHILIPS                       82S157
PHILIPS                       PLS157
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
_____________________________________________________________
Device Notes:
1.   Registers may be used as either D-type or JK-type, but
     not both (no dynamic conversion).
2.   The output enable buffer for all registers is always
     controlled by pin 11.
3.   The load control term (for loading registers from the
     output pins) is not supported.
4.   The product term that drives the register control
     buffer is fixed and may not be accessed to drive the
     complement array.
%%
%F159
F159 Architecture
Mnemonic: F159                Mnemonic: DIP
Pin Count: 20             Total Product Terms:   43
Extensions: OE D AR AP J K CA
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
PHILIPS                       82S159
PHILIPS                       PLS159
PHILIPS                       PLS159A
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
_____________________________________________________________
Device Notes:
1.   Registers may be used as either D-type or JK-type, but
     not both (no dynamic conversion).
2.   The output enable buffer for all registers is always
     controlled by pin 11.
3.   The load control term (for loading registers from the
     output pins) is not supported.
4.   The product term that drives the register control
     buffer is fixed and may not be accessed to drive the
     complement array.
%%
%F161
F161 Architecture
Mnemonic: F161                Mnemonic: DIP
Pin Count: 24             Total Product Terms:   48
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
PHILIPS                       82S161
PHILIPS                       PLS161
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
%%
%F162
F162 Architecture
Mnemonic: F162                Mnemonic: DIP
Pin Count: 24             Total Product Terms:    5
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
PHILIPS                       82S162
PHILIPS                       PLS162
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
%%
%F163
F163 Architecture
Mnemonic: F163                Mnemonic: DIP
Pin Count: 24             Total Product Terms:    9
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
PHILIPS                       82S163
PHILIPS                       PLS163
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
%%
%F167
F167 Architecture
Mnemonic: F167                Mnemonic: DIP
Pin Count: 24             Total Product Terms:   48
Extensions: S R CA OE AP
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       PLS167A/B
PHILIPS                       82S167
PHILIPS                       82S167A
PHILIPS                       PLS167
PHILIPS                       PLS167A
TI                            N82S167A
TI                            TIB82S167B
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
%%
%F167lcc
F167lcc Architecture
Mnemonic: F167lcc             Mnemonic: PLCC
Pin Count: 28             Total Product Terms:   48
Extensions: S R CA OE AP
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       PLS167A/B
PHILIPS                       82S167
PHILIPS                       82S167A
PHILIPS                       PLS167
PHILIPS                       PLS167A
TI                            N82S167A
TI                            TIB82S167B
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
%%
%F168
F168 Architecture
Mnemonic: F168                Mnemonic: DIP
Pin Count: 24             Total Product Terms:   48
Extensions: S R CA OE AP
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       PLS168A/B
PHILIPS                       82S168
PHILIPS                       PLS168
PHILIPS                       PLS168A
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
%%
%F168lcc
F168lcc Architecture
Mnemonic: F168lcc             Mnemonic: PLCC
Pin Count: 28             Total Product Terms:   48
Extensions: S R CA OE AP
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       PLS168A/B
PHILIPS                       82S168
PHILIPS                       PLS168
PHILIPS                       PLS168A
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
%%
%F16V8
F16V8 Architecture
Mnemonic: F16V8               Mnemonic: DIP
Pin Count: 20             Total Product Terms:   72
Extensions: OE D
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
PHILIPS                       PLC16V8
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
_____________________________________________________________
Device Notes:
1.  This device emulates two different PAL architectures
    with their flexible output macro configuration. When
    this device mnemonic is used, the device parameters for
    the proper sub-mode are automatically selected according
    to the following:

A.  Registered Mode             Mnemonic: F16V8D
    Specifying any output pin as registered invokes the
    registered mode (D). Specifying any output enable term
    for a nonregistered pin invokes the registered mode (D).

B.  Small Mode                  Mnemonic: F16V8S
    If neither of the above conditions are met, the device
    type defaults to the small mode (S).

2.  Either the automatic selection mechanism or the device
    mnemonic for the specific sub-mode may be used.
%%
%F173
F173 Architecture
Mnemonic: F173                Mnemonic: DIP
Pin Count: 24             Total Product Terms:   42
Extensions: OE
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
GOULD                         PEEL173
ICT                           PEEL173
PHILIPS                       82S173
PHILIPS                       PLS173
PHILIPS                       PLUS173B/D
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s): 24                    GND(s): 12
Input Only: 1  2  3  4  5  6  7  8  9  10  11  13
Output Only:
Input/Output: 14  15  16  17  18  19  20  21  22  23
%%
%F173lcc
F173lcc Architecture
Mnemonic: F173lcc             Mnemonic: PLCC
Pin Count: 28             Total Product Terms:   42
Extensions: OE
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
GOULD                         PEEL173
ICT                           PEEL173
PHILIPS                       82S173
PHILIPS                       PLS173
PHILIPS                       PLUS173B/D
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
%%
%F179
F179 Architecture
Mnemonic: F179                Mnemonic: DIP
Pin Count: 24             Total Product Terms:   43
Extensions: OE D AR AP J K CA
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
PHILIPS                       82S179
PHILIPS                       PLS179
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
_____________________________________________________________
Device Notes:
1.   Registers may be used as either D-type or JK-type, but
     not both (no dynamic conversion).
2.   The output enable buffer for all registers is always
     controlled by pin 13.
3.   The load control term (for loading registers from the
     output pins) is not supported.
4.   The product term that drives the register control
     buffer is fixed and may not be accessed to drive the
     complement array.
%%
%F179
F179 Architecture
Mnemonic: F179                Mnemonic: PLCC
Pin Count: 28            Total Product Terms:   43
Extensions: OE D AR AP J K CA
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
PHILIPS                       82S179
PHILIPS                       PLS179
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
_____________________________________________________________
Device Notes:
1.   Registers may be used as either D-type or JK-type, but
     not both (no dynamic conversion).
2.   The output enable buffer for all registers is always
     controlled by pin 13.
3.   The load control term (for loading registers from the
     output pins) is not supported.
4.   The product term that drives the register control
     buffer is fixed and may not be accessed to drive the
     complement array.
%%
%F18V8Z
F18V8Z Architecture
Mnemonic: F18V8Z              Mnemonic: DIP
Pin Count: 20             Total Product Terms:   72
Extensions: OE D AR SP
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
ATMEL                         AT18V8Z
PHILIPS                       PLC18V8Z
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
_____________________________________________________________
Device Notes:
1.  This device emulates two different PAL architectures
    with their flexible output macro configuration. When
    this device mnemonic is used, the device parameters for
    the proper sub-mode are automatically selected according
    to the following:

A.  Registered Mode             Mnemonic: F18V8ZD
    Specifying any output pin as registered invokes the
    registered mode (D). Specifying any output enable term
    for a nonregistered pin invokes the registered mode (D).

B.  Small Mode                  Mnemonic: F18V8ZS
    If neither of the above conditions are met, the device
    type defaults to the small mode (S).

2.  Either the automatic selection mechanism or the device
    mnemonic for the specific sub-mode may be used.
%%
%F20V8
F20V8 Architecture
Mnemonic: F20V8               Mnemonic: DIP
Pin Count: 24             Total Product Terms:   72
Extensions: OE D
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
PHILIPS                       PLC20V8
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
_____________________________________________________________
Device Notes:
1.  This device emulates two different PAL architectures
    with their flexible output macro configuration. When
    this device mnemonic is used, the device parameters for
    the proper sub-mode are automatically selected according
    to the following:

A.  Registered Mode             Mnemonic: F20V8D
    Specifying any output pin as registered invokes the
    registered mode (D). Specifying any output enable term
    for a nonregistered pin invokes the registered mode (D).

B.  Small Mode                  Mnemonic: F20V8S
    If neither of the above conditions are met, the device
    type defaults to the small mode (S).

2.  Either the automatic selection mechanism or the device
    mnemonic for the specific sub-mode may be used.
%%
%F253
F253 Architecture
Mnemonic: F253                Mnemonic: DIP
Pin Count: 20             Total Product Terms:   42
Extensions: OE
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
GOULD                         PEEL253
ICT                           PEEL253
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s): 20                    GND(s): 10
Input Only: 1  2  3  4  5  6  7  8
Output Only:
Input/Output: 9  11  12  13  14  15  16  17  18  19
%%
%F2552
F2552 Architecture
Mnemonic: F2552               Mnemonic: DIP
Pin Count: 68             Total Product Terms: 226
Extensions: D J K OE CK AP AR DQ
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
PHILIPS                       PML2552
_____________________________________________________________
Clock Pin(s): 20  21  22  23  Common OE(s):
              24  36  56  65
VCC(s): 4  27  38  55         GND(s): 15  32  49  66
Input Only: 8  9  10  11  12  13  14  16  17  20  21  22
            23  24  26  28  29  30  31  33  34  35  37  39
            40  41  42  43  44  45
Output Only:
Input/Output: 1  2  3  5  6  7  46  47  48  50  51  52  53
              54  57  58  59  60  61  62  63  64  67  68
%%
%F273
F273 Architecture
Mnemonic: F273                Mnemonic: DIP
Pin Count: 24             Total Product Terms:   42
Extensions: OE
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
GOULD                         PEEL273
ICT                           PEEL273
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s): 24                    GND(s): 12
Input Only: 1  2  3  4  5  6  7  8  9  10  11  13
Output Only:
Input/Output: 14  15  16  17  18  19  20  21  22  23
%%
%F2852
F2852 Architecture
Mnemonic: F2852               Mnemonic: DIP
Pin Count: 84             Total Product Terms: 226
Extensions: D J K OE CK AP AR DQ
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
PHILIPS                       PML2852
_____________________________________________________________
Clock Pin(s): 24  26  27  28  Common OE(s):
              44  68  81
VCC(s): 4  25  33  46  67     GND(s): 19  40  61  82
Input Only: 12  13  14  15  16  17  18  20  21  24  26  27
            28  30  31  32  34  35  36  37  38  39  41  42
            43  45  47  48  49
Output Only: 8  9  10  11  50  51  52  53  54  55  56  57
             71  72  73  74
Input/Output: 1  2  3  5  6  7  69  70  75  76  77  78  79
              80  83  84
%%
%F30K12
F30K12 Architecture
Mnemonic: F30K12              Mnemonic: DIP
Pin Count: 28             Total Product Terms:   72
Extensions: S R CA OE AP AR OBS CKMUX
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       PLS30K12
_____________________________________________________________
Clock Pin(s): 1  4            Common OE(s):
VCC(s): 28                    GND(s): 14
Input Only: 2  3  4  5  6  7  21  22  23  24  25  26  27
Output Only: 8  9  10  11  12  13  15  16  17  18  19  20
Input/Output:
%%
%F30S16
F30S16 Architecture
Mnemonic: F30S16              Mnemonic: DIP
Pin Count: 28             Total Product Terms:   71
Extensions: S R CA OE AP AR OBS DQ CKMUX
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       PLS30S16
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
%%
%F405
F405 Architecture
Mnemonic: F405                Mnemonic: DIP
Pin Count: 28             Total Product Terms:   64
Extensions: J K S R CA OE AP AR CKMUX OEMUX
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
PHILIPS                       PLUS405
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
%%
%F415
F415 Architecture
Mnemonic: F415                Mnemonic: DIP
Pin Count: 28             Total Product Terms:   68
Extensions: J K CA OE AP AR CKMUX OEMUX APMUX ARMUX
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
ATMEL                         ATS415
PHILIPS                       PLC415
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
%%
%F42VA12
F42VA12 Architecture
Mnemonic: F42VA12             Mnemonic: DIP
Pin Count: 24             Total Product Terms:   105
Extensions: OE D AR AP J K CA OEMUX CK IO
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
ATMEL                         ATS42VA12
PHILIPS                       PLC42VA12
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
%%
%F42VA12lcc
F42VA12lcc Architecture
Mnemonic: F42VA12lcc          Mnemonic: PLCC
Pin Count: 28             Total Product Terms:   105
Extensions: OE D AR AP J K CA OEMUX CK IO
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
ATMEL                         ATS42VA12
PHILIPS                       PLC42VA12
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
%%
%F473
F473 Architecture
Mnemonic: F473                Mnemonic: DIP
Pin Count: 24             Total Product Terms:   24
Extensions: OE
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
PHILIPS                       PLC473
PHILIPS                       PLHS473
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
%%
%F473lcc
F473lcc Architecture
Mnemonic: F473lcc             Mnemonic: PLCC
Pin Count: 28             Total Product Terms:   24
Extensions: OE
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
PHILIPS                       PLC473
PHILIPS                       PLHS473
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
%%
%F48N22
F48N22 Architecture
Mnemonic: F48N22              Mnemonic: DIP
Pin Count: 68             Total Product Terms:   73
Extensions: OE
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
PHILIPS                       PHD48N22
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
%%
%F501
F501 Architecture
Mnemonic: F501                Mnemonic: DIP
Pin Count: 52             Total Product Terms:  112
Extensions: OE CA
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
PHILIPS                       PLHS501
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
_____________________________________________________________
Device Notes:
1.  The F501 contains a NAND array architecture. The NAND
    gates must be defined as complement array nodes.

2.  Although there is only one product term for each output
    pin, multiple product term output can be implemented
    using DeMorgan's algorithm and NAND nodes.

    For example, to implement the following logical
    function:

    X = (a & b)
      # (c & d)
      # (e & f);

    Define as follows:

    Pin 19 = X;

    Pinnode 53 = !X1;
    Pinnode 54 = !X2;
    Pinnode 55 = !X3;

    X = !(!X1 & !X2 & !X3);
    X1.ca = a & b;
    X2.ca = c & d;
    X3.ca = e & f;
%%
%F502
F502 Architecture
Mnemonic: F502                Mnemonic: DIP
Pin Count: 64             Total Product Terms:  144
Extensions: OE CA D S R AR CK
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
PHILIPS                       PLHS502
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
_____________________________________________________________
Device Notes:
1.  The F502 contains a NAND array architecture. The NAND
    gates must be defined as complement array nodes.

2.  Although there is only one product term for each output
    pin, multiple product term output can be implemented
    using DeMorgan's algorithm and NAND nodes.

    For example, to implement the following logical
    function:

    X = (a & b)
      # (c & d)
      # (e & f);

    Define as follows:

    Pin 19 = X;

    Pinnode 81 = !X1;
    Pinnode 82 = !X2;
    Pinnode 83 = !X3;

    X = !(!X1 & !X2 & !X3);
    X1.ca = a & b;
    X2.ca = c & d;
    X3.ca = e & f;
%%
%F506
F506 Architecture
Mnemonic: F506                Mnemonic: DIP
Pin Count: 24             Total Product Terms:   98
Extensions: S R CA OE CKMUX
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
TI                            TIBPLS506A
_____________________________________________________________
Clock Pin(s): 1               Common OE(s): 17
VCC(s): 24                    GND(s): 12
Input Only: 2  3  4  5  6  7  17  18  19  20  21  22  23
Output Only: 8  9  10  11  13  14  15  16
Input/Output:
_____________________________________________________________
Device Notes:
1.  The registered clock polarity is set by writing one
    .CKMUX expression for all registers used in the design.
    By default, the clock is treated as positive-edge
    triggered.

2.  Pin 17 (dip, 20 lcc) can be programmed to function
    as input only or input and output enable. The
    following examples show how to do this:

    Input only                  Input/Output enable
                      
    Pin  1 = clk;               Pin  1 = clk;
    Pin 17 = a;                 Pin 17 = a;
    Pin 16 = x;                 Pin 16 = x;
    Pin 24 = VCC24;             Pin  2 = b;

    x.s = a;                    x.s = b;
    x.r = !a;                   x.r = !b;
    x.ckmux = clk;              x.ckmux = clk;
    /* set OE always ON */      /* set active low OE */
    x.oemux = VCC24;            x.oemux = !a;

    The default (not specifying an OE) is input/output
    enable.
%%
%F506lcc
F506lcc Architecture
Mnemonic: F506lcc             Mnemonic: PLCC
Pin Count: 28             Total Product Terms:   98
Extensions: S R CA OE CKMUX
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
TI                            TIBPLS506A
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
_____________________________________________________________
Device Notes:
1.  The registered clock polarity is set by writing one
    .CKMUX expression for all registers used in the design.
    By default, the clock is treated as positive-edge
    triggered.

2.  Pin 17 (dip, 20 lcc) can be programmed to function
    as input only or input and output enable. The
    following examples show how to do this:

    Input only                  Input/Output enable
                      
    Pin  1 = clk;               Pin  1 = clk;
    Pin 17 = a;                 Pin 17 = a;
    Pin 16 = x;                 Pin 16 = x;
    Pin 24 = VCC24;             Pin  2 = b;

    x.s = a;                    x.s = b;
    x.r = !a;                   x.r = !b;
    x.ckmux = clk;              x.ckmux = clk;
    /* set OE always ON */      /* set active low OE */
    x.oemux = VCC24;            x.oemux = !a;

    The default (not specifying an OE) is input/output
    enable.
%%
%F507
F507 Architecture
Mnemonic: F507                Mnemonic: DIP
Pin Count: 24             Total Product Terms:   80
Extensions: S R OE CKMUX CNT
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
TI                            TIBPSG507A
_____________________________________________________________
Clock Pin(s): 1               Common OE(s): 17
VCC(s): 24                    GND(s): 12
Input Only: 2  3  4  5  6  7  17  18  19  20  21  22  23
Output Only: 8  9  10  11  13  14  15  16
Input/Output:
_____________________________________________________________
Device Notes:
1.  The register and counter clock polarity are set by
    writing one .CKMUX expression for all registers and
    counter inputs used in the design. By default, the clock
    is treated as positive-edge triggered.
2.  The built-in counter input nodes are defined using the
    NODE or PINNODE statements, and the .CNT extension. The
    counter clear and hold controls are defined using the
    NODE or PINNODE statements and writing either
    combinatorial or S-R registered expressions.
3.  CSIM generates the counter inputs automatically, based
    on the counter control logic.
%%
%F507lcc
F507lcc Architecture
Mnemonic: F507lcc             Mnemonic: PLCC
Pin Count: 28             Total Product Terms:   80
Extensions: S R OE CKMUX CNT
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
TI                            TIBPSG507A
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
_____________________________________________________________
Device Notes:
1.  The register and counter clock polarity are set by
    writing one .CKMUX expression for all registers and
    counter inputs used in the design. By default, the clock
    is treated as positive-edge triggered.
2.  The built-in counter input nodes are defined using the
    NODE or PINNODE statements, and the .CNT extension. The
    counter clear and hold controls are defined using the
    NODE or PINNODE statements and writing either
    combinatorial or S-R registered expressions.
3.  CSIM generates the counter inputs automatically, based
    on the counter control logic.
%%
%F529
F529 Architecture
Mnemonic: F529                Mnemonic: DIP
Pin Count: 20             Total Product Terms:    8
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
TI                            TIBFPGA529
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
%%
%F7024
F7024 Architecture
Mnemonic: F7024               Mnemonic: DIP
Pin Count:24              Total Product Terms: 80
Extensions: OE IO D T J K AR AP CK IOD IOL DQ LQ FFM
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
ICT                           PEEL7024
_____________________________________________________________
Clock Pin(s): 1  13          Common OE(s):
VCC(s): 24                   GND(s): 12
Input Only: 1  13
Output Only:
Input/Output: 2  3  4  5  6  7  8  9  10  11  14  15  16  17
              18  19  20  21  22  23
_____________________________________________________________
Device Notes:
1.  The simulation of FFM (flip-flop mode) is not supported.
%%
%F7024
F7024 Architecture
Mnemonic: F7024               Mnemonic: PLCC
Pin Count:28              Total Product Terms: 80
Extensions: OE IO D T J K AR AP CK IOD IOL DQ LQ FFM
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
ICT                           PEEL7024
_____________________________________________________________
Clock Pin(s):                Common OE(s):
VCC(s):                      GND(s):
Input Only:
Output Only:
Input/Output:

_____________________________________________________________
Device Notes:
1.  The simulation of FFM (flip-flop mode) is not supported.
%%
%F7128
F7128 Architecture
Mnemonic: F7128               Mnemonic: DIP
Pin Count:28              Total Product Terms: 68
Extensions: OE IO D T J K AR AP CK IOD IOL DQ LQ FFM
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
ICT                           PEEL7128
_____________________________________________________________
Clock Pin(s): 1  28          Common OE(s):
VCC(s): 7                    GND(s): 21
Input Only: 1  2  3  4  5  6  8  9  10  11  12  13  14  28
Output Only:
Input/Output: 15  16  17  18  19  20  22  23  24  25  26  27
_____________________________________________________________
Device Notes:
1.  The simulation of FFM (flip-flop mode) is not supported.
%%
%F7140
F7140 Architecture
Mnemonic: F7140               Mnemonic: DIP
Pin Count:40              Total Product Terms: 120
Extensions: OE IO D T J K AR AP CK IOD IOL DQ LQ FFM
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
ICT                           PEEL7140
_____________________________________________________________
Clock Pin(s): 1  21          Common OE(s):
VCC(s): 40                   GND(s): 20
Input Only: 1  2  3  4  17  18  19  21  22  23  24  37  38
            39
Output Only:
Input/Output: 5  6  7  8  9  10  11  12  13  14  15  16  25
              26  27  28  29  30  31  32  33  34  35  36
_____________________________________________________________
Device Notes:
1.  The simulation of FFM (flip-flop mode) is not supported.
%%
%F7140lcc
F7140lcc Architecture
Mnemonic: F7140lcc            Mnemonic: PLCC
Pin Count:44              Total Product Terms: 120
Extensions: OE IO D T J K AR AP CK IOD IOL DQ LQ FFM
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
ICT                           PEEL7140
_____________________________________________________________
Clock Pin(s):                Common OE(s):
VCC(s):                      GND(s):
Input Only:
Output Only:
Input/Output:
_____________________________________________________________
Device Notes:
1.  The simulation of FFM (flip-flop mode) is not supported.
%%
%F839
F839 Architecture
Mnemonic: F839                Mnemonic: DIP
Pin Count: 24             Total Product Terms:   32
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
NATIONAL                      87X839
NATIONAL                      87X840
TI                            TIFPLA839
TI                            TIFPLA840
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
%%
%F9800
F9800 Architecture
Mnemonic: F9800               Mnemonic: DIP
Pin Count: 20             Total Product Terms:   45
Extensions: D OE
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
TOSHIBA                       TC9800P
TOSHIBA                       TC9801P
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
%%
%G16V8
G16V8 Architecture
Mnemonic: G16V8               Mnemonic: DIP/PLCC
Pin Count: 20             Total Product Terms:   64
Extensions: OE D
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       PALCE16V8/4
AMD/MMI                       PALCE16V8H/Q
AMD/MMI                       PALCE16V8Z
LATTICE                       GAL16V8
NATIONAL                      GAL16V8
SGS-THOM.                     GAL16V8
VLSI                          VP16V8E
_____________________________________________________________
Clock Pin(s): 1               Common OE(s): 11
VCC(s): 20                    GND(s): 10
Input Only: 2  3  4  5  6  7  8  9
Output Only:
Input/Output: 12  13  14  15  16  17  18  19
_____________________________________________________________
Device Notes:
1.  This device emulates three different PAL architectures
    with their flexible output macro configuration. When
    this device mnemonic is used, the device parameters for
    the proper sub-mode are automatically selected according
    to the following:

A.  Registered Mode             Mnemonic: G16V8MS
    This mode is automatically chosen when the PLD source
    file has registered output. In the registered mode,
    specifying an output enable term for a registered
    output pin is not flagged as an error by the compiler or
    simulator.

    Input only      Output only    Input/Output
    ----------      -----------    ------------
     2, 3, 4,                       12, 13, 14,
     5, 6, 7,                       15, 16, 17,
     8, 9                           18, 19

    Pin 1 = common clock     Pin 11 = common output enable

    In this mode, the output enable control for registered
    pins is common to pin 11.

B.  Complex Mode                Mnemonic: G16V8MA
    This mode is automatically chosen when the PLD source
    file has an output enable term for a non-registered pin
    and/or combinatorial feedback.

    Input only     Output only    Input/Output
    ----------     -----------    ------------
     1, 2, 3,         12, 19       13, 14, 15,
     4, 5, 6,                      16, 17, 18
     7, 8, 9,
     11

C.  Simple Mode (Default)       Mnemonic: G16V8S
    If none of the above are met, the device type defaults
    to the small mode. In this mode, the Input/Output pins
    are configured as either Input Only or Output only
    (that is, no feedback can occur).


    Input only     Output only    Input/Output
    ----------     -----------    ------------
     1, 2, 3,        15, 16        12, 13, 14,
     4, 5, 6,                      17, 18, 19
     7, 8, 9,
     11

2.  Either the automatic selection mechanism or the device
    mnemonic for the specific sub-mode desired can be used.
%%
%G16V8A
G16V8A Architecture
Mnemonic: G16V8A              Mnemonic: DIP
Pin Count: 20             Total Product Terms:   64
Extensions: OE D
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
ATMEL                         ATF16V8B/L
LATTICE                       GAL16V8A
LATTICE                       GAL16V8B
LATTICE                       GAL16V8C/Z
LATTICE                       GAL16LV8
NATIONAL                      GAL16VA/QS/-7
SGS-THOM.                     GAL16V8A
_____________________________________________________________
%%
%G16V8H
G16V8H Architecture
Mnemonic: G16V8H              Mnemonic: DIP
Pin Count: 24             Total Product Terms:   64
Extensions: OE D T IOL LQ LE TEC
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       PALCE16V8HD
_____________________________________________________________
Clock Pin(s): 1               Common OE(s): 10
VCC(s): 11  18  24            GND(s): 12  17  21
Input Only: 2  3  4  5  6  7  8  9
Output Only:
Input/Output: 13  14  15  16  19  20  22  23
_____________________________________________________________
Device Notes:
1.  This device emulates three different PAL architectures
    with their flexible output macro configuration. When
    this device mnemonic is used, the device parameters for
    the proper sub-mode are automatically selected according
    to the following:

A.  Registered Mode             Mnemonic: G16V8HMS
    This mode is automatically chosen when the PLD source
    file has registered output. In the registered mode,
    specifying an output enable term for a registered
    output pin is not flagged as an error by the compiler or
    simulator.

    Input only      Output only    Input/Output
    ----------      -----------    ------------
     2, 3, 4,                       13, 14, 15,
     5, 6, 7,                       16, 19, 20,
     8, 9                           22, 23

    Pin 1 = common clock     Pin 10 = common output enable

    In this mode, the output enable control for registered
    pins is common to pin 10.

B.  Complex Mode                Mnemonic: G16V8HMA
    This mode is automatically chosen when the PLD source
    file has an output enable term for a non-registered pin
    and/or combinatorial feedback.

    Input only     Output only    Input/Output
    ----------     -----------    ------------
     1, 2, 3,         13, 23       14, 15, 16,
     4, 5, 6,                      19, 20, 22
     7, 8, 9,
     10

C.  Simple Mode (Default)       Mnemonic: G16V8HS
    If none of the above are met, the device type defaults
    to the small mode. In this mode, the Input/Output pins
    are configured as either Input Only or Output only
    (that is, no feedback can occur).


    Input only     Output only    Input/Output
    ----------     -----------    ------------
     1, 2, 3,        16, 19        13, 14, 15,
     4, 5, 6,                      20, 22, 23
     7, 8, 9,
     10

2.  Either the automatic selection mechanism or the device
    mnemonic for the specific sub-mode desired can be used.

3.  The 64mA output pins can be programmed to behave as
    either Totem-pole or Open-drain (default is Totem-pole).
    Use the .TEC extension on each output and assign it a
    'b'1.  This allows the output to be used as Open-drain.
        Ex.  OUTPUT.TEC = 'b'1;   /* Set to Open-drain */

4.  Each input or I/O pin can be configured as either a
    direct input or a transparent latch.  The latch requires
    the .LQ extension to be added to the variable name.
%%
%G16V8Hlcc
G16V8Hlcc Architecture
Mnemonic: G16V8Hlcc           Mnemonic: PLCC
Pin Count: 28             Total Product Terms:   64
Extensions: OE D T IOL LQ LE TEC
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       PALCE16V8HD
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
_____________________________________________________________
Device Notes:
1.  This device emulates three different PAL architectures
    with their flexible output macro configuration. When
    this device mnemonic is used, the device parameters for
    the proper sub-mode are automatically selected according
    to the following:

A.  Registered Mode             Mnemonic: G16V8HMS
    This mode is automatically chosen when the PLD source
    file has registered output. In the registered mode,
    specifying an output enable term for a registered
    output pin is not flagged as an error by the compiler or
    simulator.

    Input only      Output only    Input/Output
    ----------      -----------    ------------
     2, 3, 4,                       13, 14, 15,
     5, 6, 7,                       16, 19, 20,
     8, 9                           22, 23

    Pin 1 = common clock     Pin 10 = common output enable

    In this mode, the output enable control for registered
    pins is common to pin 10.

B.  Complex Mode                Mnemonic: G16V8HMA
    This mode is automatically chosen when the PLD source
    file has an output enable term for a non-registered pin
    and/or combinatorial feedback.

    Input only     Output only    Input/Output
    ----------     -----------    ------------
     1, 2, 3,         13, 23       14, 15, 16,
     4, 5, 6,                      19, 20, 22
     7, 8, 9,
     10

C.  Simple Mode (Default)       Mnemonic: G16V8HS
    If none of the above are met, the device type defaults
    to the small mode. In this mode, the Input/Output pins
    are configured as either Input Only or Output only
    (that is, no feedback can occur).


    Input only     Output only    Input/Output
    ----------     -----------    ------------
     1, 2, 3,        16, 19        13, 14, 15,
     4, 5, 6,                      20, 22, 23
     7, 8, 9,
     10

2.  Either the automatic selection mechanism or the device
    mnemonic for the specific sub-mode desired can be used.

3.  The 64mA output pins can be programmed to behave as
    either Totem-pole or Open-drain (default is Totem-pole).
    Use the .TEC extension on each output and assign it a
    'b'1.  This allows the output to be used as Open-drain.
        Ex.  OUTPUT.TEC = 'b'1;   /* Set to Open-drain */

4.  Each input or I/O pin can be configured as either a
    direct input or a transparent latch.  The latch requires
    the .LQ extension to be added to the variable name.
%%
%G16VP8
G16VP8 Architecture
Mnemonic: G16VP8              Mnemonic: DIP
Pin Count: 20             Total Product Terms:   64
Extensions: OE D TEC
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
LATTICE                       GAL16VP8
_____________________________________________________________
Clock Pin(s): 1               Common OE(s): 10
VCC(s): 5                     GND(s): 15
Input Only: 2  3  4  6  7  8  9  20
Output Only:
Input/Output: 11  12  13  14  16  17  18  19
_____________________________________________________________
Device Notes:
1.  This device emulates three different PAL architectures
    with their flexible output macro configuration. When
    this device mnemonic is used, the device parameters for
    the proper sub-mode are automatically selected according
    to the following:

A.  Registered Mode             Mnemonic: G16VP8MS
    This mode is automatically chosen when the PLD source
    file has registered output. In the registered mode,
    specifying an output enable term for a registered
    output pin is not flagged as an error by the compiler or
    simulator.

    Input only      Output only    Input/Output
    ----------      -----------    ------------
     2, 3, 4,                       11, 12, 13,
     6, 7, 8,                       14, 16, 17,
     9, 20                          18, 19

    Pin 1 = common clock     Pin 10 = common output enable

    In this mode, the output enable control for registered
    pins is common to pin 10.

B.  Complex Mode                Mnemonic: G16VP8MA
    This mode is automatically chosen when the PLD source
    file has an output enable term for a non-registered pin
    and/or combinatorial feedback.

    Input only     Output only    Input/Output
    ----------     -----------    ------------
     1, 2, 3,         11, 19       12, 13, 14,
     4, 6, 7,                      16, 17, 18
     8, 9, 10,
     20

C.  Simple Mode (Default)       Mnemonic: G16VP8S
    If none of the above are met, the device type defaults
    to the small mode. In this mode, the Input/Output pins
    are configured as either Input Only or Output only
    (that is, no feedback can occur).


    Input only     Output only    Input/Output
    ----------     -----------    ------------
     1, 2, 3,        14, 16        11, 12, 13,
     4, 6, 7,                      17, 18, 19
     8, 9, 10,
     20

2.  Either the automatic selection mechanism or the device
    mnemonic for the specific sub-mode desired can be used.

3.  The 64mA output drive on the I/O pins can be programmed
    to behave as totem-pole or open collector outputs.  The
    default is totem-pole output.  To obtain open collector
    outputs, the variable must be defined with a .TEC
    extension and set equal to 'b'0.
        Ex.  OUTPUT.TEC = 'b'0;
%%
%G16Z8
G16Z8 Architecture
Mnemonic: G16Z8               Mnemonic: DIP
Pin Count: 24             Total Product Terms:   64
Extensions: OE D
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
LATTICE                       GAL16Z8
SGS-THOM.                     GAL16Z8
_____________________________________________________________
Clock Pin(s): 1               Common OE(s): 13
VCC(s): 24                    GND(s): 12
Input Only: 3  4  5  6  7  8  9  10  13
Output Only:
Input/Output: 15  16  17  18  19  20  21  22
Unused: 2  11  14  23
%%
%G16Z8lcc
G16Z8lcc Architecture
Mnemonic: G16Z8lcc            Mnemonic: PLCC
Pin Count: 28             Total Product Terms:   64
Extensions: OE D
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
LATTICE                       GAL16Z8
SGS-THOM.                     GAL16Z8
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
Unused:
%%
%G18V10
G18V10 Architecture
Mnemonic: G18V10              Mnemonic: DIP
Pin Count: 20             Total Product Terms:   96
Extensions: OE D AR SP
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
LATTICE                       GAL18V10
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
%%
%G20RA10
G20RA10 Architecture
Mnemonic: G20RA10             Mnemonic: DIP
Pin Count: 24             Total Product Terms:   80
Extensions: OE D AR AP CK IO
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
LATTICE                       GAL20RA10(UES)
NATIONAL                      GAL20RA10
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
%%
%G20RA10lcc
G20RA10lcc Architecture
Mnemonic: G20RA10lcc          Mnemonic: PLCC
Pin Count: 24             Total Product Terms:   80
Extensions: OE D AR AP CK IO
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
LATTICE                       GAL20RA10(UES)
NATIONAL                      GAL20RA10
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
%%
%G20V8
G20V8 Architecture
Mnemonic: G20V8               Mnemonic: DIP
Pin Count: 24             Total Product Terms:   20
Extensions: OE D
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       PALCE20V8/4
AMD/MMI                       PALCE20V8H/Q
LATTICE                       GAL20V8
LATTICE                       RAL14H8
LATTICE                       RAL16H6
LATTICE                       RAL18H4
LATTICE                       RAL20H2
LATTICE                       RAL20H8
NATIONAL                      GAL20V8
NATIONAL                      PAL14H8/20V8
NATIONAL                      PAL16H6/20V8
NATIONAL                      PAL18H4/20V8
NATIONAL                      PAL20H2/20V8
NATIONAL                      PAL20H8/20V8
SGS-THOM.                     GAL20V8
SGS-THOM.                     RAL14H8
SGS-THOM.                     RAL16H6
SGS-THOM.                     RAL18H4
SGS-THOM.                     RAL20H2
SGS-THOM.                     RAL20H8
VLSI                          VP20V8E
_____________________________________________________________
Clock Pin(s): 1               Common OE(s): 13
VCC(s): 24                    GND(s): 12
Input Only: 2  3  4  5  6  7  8  9  10  11  14  23
Output Only:
Input/Output: 15  16  17  18  19  20  21  22
_____________________________________________________________
Device Notes:
1.  This device emulates three different PAL architectures
    with their flexible output macro configuration. When
    this device mnemonic is used, the device parameters for
    the proper sub-mode are automatically selected according
    to the following:

A.  Registered Mode             Mnemonic: G20V8MS
    This mode is automatically chosen when the PLD source
    file has registered output. In the registered mode,
    specifying an output enable term for a registered
    output pin is not flagged as an error by the compiler or
    simulator.

    Input only      Output only    Input/Output
    ----------      -----------    ------------
     2, 3, 4,                       15, 16, 17,
     5, 6, 7,                       18, 19, 20,
     8, 9, 10,                      21, 22
     11, 14, 23

    Pin 1 = common clock     Pin 13 = common output enable
    In this mode, the output enable control for registered
    pins is common to pin 13.

B.  Complex Mode                Mnemonic: G20V8MA
    This mode is automatically chosen when the PLD source
    file has an output enable term for a non-registered pin
    and/or combinatorial feedback.

    Input only     Output only    Input/Output
    ----------     -----------    ------------
     1, 2, 3,         15, 22        16, 17, 18,
     4, 5, 6,                       19, 20, 21
     7, 8, 9,
     10, 11, 13,
     14, 23

C.  Simple Mode (Default)       Mnemonic: G20V8S
    If none of the above are met, the device type defaults
    to the small mode. In this mode, the Input/Output pins
    are configured as either Input Only or Output only
    (that is, no feedback can occur).

    Input only     Output only   Input/Output
    ----------     -----------   ------------
     1, 2, 3,        18, 19       15, 16, 17,
     4, 5, 6,                     20, 21, 22
     7, 8, 9,
     10, 11, 13,
     14, 23

2.  Either the automatic selection mechanism or the device
    mnemonic for the specific sub-mode desired can be used.
%%
%G20V8lcc
G20V8lcc Architecture
Mnemonic: G20V8lcc            Mnemonic: PLCC
Pin Count: 28             Total Product Terms:   20
Extensions: OE D
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       PALCE20V8/4
AMD/MMI                       PALCE20V8H/Q
LATTICE                       GAL20V8
LATTICE                       RAL14H8
LATTICE                       RAL16H6
LATTICE                       RAL18H4
LATTICE                       RAL20H2
LATTICE                       RAL20H8
NATIONAL                      GAL20V8
NATIONAL                      PAL14H8/20V8
NATIONAL                      PAL16H6/20V8
NATIONAL                      PAL18H4/20V8
NATIONAL                      PAL20H2/20V8
NATIONAL                      PAL20H8/20V8
SGS-THOM.                     GAL20V8
SGS-THOM.                     RAL14H8
SGS-THOM.                     RAL16H6
SGS-THOM.                     RAL18H4
SGS-THOM.                     RAL20H2
SGS-THOM.                     RAL20H8
VLSI                          VP20V8E
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
_____________________________________________________________
Device Notes:
1.  This device emulates three different PAL architectures
    with their flexible output macro configuration. When
    this device mnemonic is used, the device parameters for
    the proper sub-mode are automatically selected according
    to the following:

A.  Registered Mode             Mnemonic: G20V8MS
    This mode is automatically chosen when the PLD source
    file has registered output. In the registered mode,
    specifying an output enable term for a registered
    output pin is not flagged as an error by the compiler or
    simulator.

    Input only      Output only    Input/Output
    ----------      -----------    ------------
     2, 3, 4,                       15, 16, 17,
     5, 6, 7,                       18, 19, 20,
     8, 9, 10,                      21, 22
     11, 14, 23

    Pin 1 = common clock     Pin 13 = common output enable
    In this mode, the output enable control for registered
    pins is common to pin 13.

B.  Complex Mode                Mnemonic: G20V8MA
    This mode is automatically chosen when the PLD source
    file has an output enable term for a non-registered pin
    and/or combinatorial feedback.

    Input only     Output only    Input/Output
    ----------     -----------    ------------
     1, 2, 3,         15, 22        16, 17, 18,
     4, 5, 6,                       19, 20, 21
     7, 8, 9,
     10, 11, 13,
     14, 23

C.  Simple Mode (Default)       Mnemonic: G20V8S
    If none of the above are met, the device type defaults
    to the small mode. In this mode, the Input/Output pins
    are configured as either Input Only or Output only
    (that is, no feedback can occur).

    Input only     Output only   Input/Output
    ----------     -----------   ------------
     1, 2, 3,        18, 19       15, 16, 17,
     4, 5, 6,                     20, 21, 22
     7, 8, 9,
     10, 11, 13,
     14, 23

2.  Either the automatic selection mechanism or the device
    mnemonic for the specific sub-mode desired can be used.
%%
%G20V8A
G20V8A Architecture
Mnemonic: G20V8A              Mnemonic: DIP
Pin Count: 24             Total Product Terms:   64
Extensions: OE D
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
ATMEL                         ATF20V8B/L
LATTICE                       GAL20V8A
LATTICE                       GAL20V8B
LATTICE                       GAL20V8C/Z
LATTICE                       GAL20LV8
NATIONAL                      GAL20V8A/QS/-7
SGS-THOM.                     GAL20V8A
_____________________________________________________________
Clock Pin(s): 1               Common OE(s): 13
VCC(s): 24                    GND(s): 12
Input Only: 2  3  4  5  6  7  8  9  10  11  14  23
Output Only:
Input/Output: 15  16  17  18  19  20  21  22
%%
%G20V8Alcc
G20V8Alcc Architecture
Mnemonic: G20V8Alcc           Mnemonic: PLCC
Pin Count: 28             Total Product Terms:   64
Extensions: OE D
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
ATMEL                         ATF20V8B/L
LATTICE                       GAL20V8A
LATTICE                       GAL20V8B
LATTICE                       GAL20V8C/Z
LATTICE                       GAL20LV8
NATIONAL                      GAL20V8A/QS/-7
SGS-THOM.                     GAL20V8A
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
%%
%G20VP8
G20VP8 Architecture
Mnemonic: G20VP8              Mnemonic: DIP
Pin Count: 24             Total Product Terms:   20
Extensions: OE D TEC
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
LATTICE                       GAL20VP8
_____________________________________________________________
Clock Pin(s): 1               Common OE(s): 12
VCC(s): 6                     GND(s): 18
Input Only: 1  2  3  4  5  7  8  9  10  11  12  13  23  24
Output Only:
Input/Output: 14  15  16  17  19  20  21  22
_____________________________________________________________
Device Notes:
1.  This device emulates three different PAL architectures
    with their flexible output macro configuration. When
    this device mnemonic is used, the device parameters for
    the proper sub-mode are automatically selected according
    to the following:

A.  Registered Mode             Mnemonic: G20VP8MS
    This mode is automatically chosen when the PLD source
    file has registered output. In the registered mode,
    specifying an output enable term for a registered
    output pin is not flagged as an error by the compiler or
    simulator.

    Input only      Output only    Input/Output
    ----------      -----------    ------------
     2, 3, 4,                       14, 15, 16,
     5, 7, 8,                       17, 19, 20,
     9, 10, 11,                     21, 22
     13, 23, 24

    Pin 1 = common clock     Pin 12 = common output enable
    In this mode, the output enable control for registered
    pins is common to pin 12.

B.  Complex Mode                Mnemonic: G20VP8MA
    This mode is automatically chosen when the PLD source
    file has an output enable term for a non-registered pin
    and/or combinatorial feedback.

    Input only     Output only    Input/Output
    ----------     -----------    ------------
     1, 2, 3,         14, 22        15, 16, 17,
     4, 5, 7,                       19, 20, 21
     8, 9, 10,
     11, 12, 13,
     23, 24

C.  Simple Mode (Default)       Mnemonic: G20VP8S
    If none of the above are met, the device type defaults
    to the small mode. In this mode, the Input/Output pins
    are configured as either Input Only or Output only
    (that is, no feedback can occur).

    Input only     Output only   Input/Output
    ----------     -----------   ------------
     1, 2, 3,        17, 19       14, 15, 16,
     4, 5, 7,                     20, 21, 22
     8, 9, 10,
     11, 12, 13,
     23, 24

2.  Either the automatic selection mechanism or the device
    mnemonic for the specific sub-mode desired can be used.

3.  The 64mA output drive on the I/O pins can be programmed
    to behave as totem-pole or open collector outputs.  The
    default is totem-pole output.  To obtain open collector
    outputs, the variable must be defined with a .TEC
    extension and set equal to 'b'0.
        Ex.  OUTPUT.TEC = 'b'0;
%%
%G20VP8lcc
G20VP8lcc Architecture
Mnemonic: G20VP8lcc           Mnemonic: PLCC
Pin Count: 28             Total Product Terms:   20
Extensions: OE D TEC
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
LATTICE                       GAL20VP8
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
_____________________________________________________________
Device Notes:
1.  This device emulates three different PAL architectures
    with their flexible output macro configuration. When
    this device mnemonic is used, the device parameters for
    the proper sub-mode are automatically selected according
    to the following:

A.  Registered Mode             Mnemonic: G20VP8MS
    This mode is automatically chosen when the PLD source
    file has registered output. In the registered mode,
    specifying an output enable term for a registered
    output pin is not flagged as an error by the compiler or
    simulator.

    Input only      Output only    Input/Output
    ----------      -----------    ------------
     2, 3, 4,                       14, 15, 16,
     5, 7, 8,                       17, 19, 20,
     9, 10, 11,                     21, 22
     13, 23, 24

    Pin 1 = common clock     Pin 12 = common output enable
    In this mode, the output enable control for registered
    pins is common to pin 12.

B.  Complex Mode                Mnemonic: G20VP8MA
    This mode is automatically chosen when the PLD source
    file has an output enable term for a non-registered pin
    and/or combinatorial feedback.

    Input only     Output only    Input/Output
    ----------     -----------    ------------
     1, 2, 3,         14, 22        15, 16, 17,
     4, 5, 7,                       19, 20, 21
     8, 9, 10,
     11, 12, 13,
     23, 24

C.  Simple Mode (Default)       Mnemonic: G20VP8S
    If none of the above are met, the device type defaults
    to the small mode. In this mode, the Input/Output pins
    are configured as either Input Only or Output only
    (that is, no feedback can occur).

    Input only     Output only   Input/Output
    ----------     -----------   ------------
     1, 2, 3,        17, 19       14, 15, 16,
     4, 5, 7,                     20, 21, 22
     8, 9, 10,
     11, 12, 13,
     23, 24

2.  Either the automatic selection mechanism or the device
    mnemonic for the specific sub-mode desired can be used.

3.  The 64mA output drive on the I/O pins can be programmed
    to behave as totem-pole or open collector outputs.  The
    default is totem-pole output.  To obtain open collector
    outputs, the variable must be defined with a .TEC
    extension and set equal to 'b'0.
        Ex.  OUTPUT.TEC = 'b'0;
%%
%G20XV10
G20XV10 Architecture
Mnemonic: G20XV10             Mnemonic: DIP
Pin Count: 24             Total Product Terms:  40
Extensions: OE D OEMUX
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
LATTICE                       GAL20XV10B
_____________________________________________________________
Clock Pin(s): 1               Common OE(s):
VCC(s): 24                    GND(s): 12
Input Only: 1  2  3  4  5  6  7  8  9  10  11  13
Output Only:
Input/Output: 14  15  16  17  18  19  20  21  22  23
_____________________________________________________________
Device Notes:
1.  The G20XV10 can emulate the following devices in the
    corresponding modes:

      Devices          G20XV10 Mode         CUPL Mnemonic
                         
       P12L10             Input               g20xv10i
       P20L10             Input               g20xv10i
       P20X10            Feedback             g20xv10f
       P20X8             Feedback             g20xv10f
       P20X4             Feedback             g20xv10f

    If one would like to force CUPL to use a specific mode
    for the design, just use the mnemonic that represents
    that mode.

2.  Each output can be configured as registered or
    combinatorial with either 3 pterms ORed together or
    4 pterms XORed together as input. The following table
    shows how to obtain the different configurations of the
    Output Logic Macrocell (OLMC):

        OLMC Configuration          Implementation in Design
                  
        Registered output
            XOR input, COE              Default
            OR input, OE pterm          Use OE extension

        Combinatorial output
            XOR input, COE              Use OEMUX extension
            OR input, OE pterm          Default

3.  If the G20XV10 device mnemonic is used, the device
    parameters for the proper sub-mode are automatically
    selected according to the following:

A.  Input mode                  Mnemonic:  g20xv10i

    This mode is automatically chosen when the PLD source
    file has combinatorial output only.

    Input Only            Output Only           Input/Output
                           
     2, 3, 4,               14, 23               15, 16, 17,
     5, 6, 7,                                    18, 19, 20
     8, 9, 10,                                   21, 22
     11

     Pin 1 can be used both as a Synchronous Clock and an
     input. Pin 13 can be used both as a Common Output
     Enable (COE) and an input.

B.  Feedback mode               Mnemonic:  g20xv10f

    This mode is automatically chosen when the PLD source
    file has registered output.

    Input Only            Output Only           Input/Output
                           
     2, 3, 4,                                    14, 15, 16,
     5, 6, 7,                                    17, 18, 19,
     8, 9, 10,                                   20, 21, 22,
     11                                          23

    Pin 1 is the Synchronous Clock
    Pin 13 is the Common Output Enable (COE)
%%
%G20XV10lcc
G20XV10lcc Architecture
Mnemonic: G20XV10lcc          Mnemonic: plcc
Pin Count: 28             Total Product Terms:  40
Extensions: OE D OEMUX
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
LATTICE                       GAL20XV10B
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
_____________________________________________________________
Device Notes:
1.  The G20XV10 can emulate the following devices in the
    corresponding modes:

      Devices          G20XV10 Mode         CUPL Mnemonic
                         
       P12L10             Input               g20xv10i
       P20L10             Input               g20xv10i
       P20X10            Feedback             g20xv10f
       P20X8             Feedback             g20xv10f
       P20X4             Feedback             g20xv10f

    If one would like to force CUPL to use a specific mode
    for the design, just use the mnemonic that represents
    that mode.

2.  Each output can be configured as registered or
    combinatorial with either 3 pterms ORed together or
    4 pterms XORed together as input. The following table
    shows how to obtain the different configurations of the
    Output Logic Macrocell (OLMC):

        OLMC Configuration          Implementation in Design
                  
        Registered output
            XOR input, COE              Default
            OR input, OE pterm          Use OE extension

        Combinatorial output
            XOR input, COE              Use OEMUX extension
            OR input, OE pterm          Default

3.  If the G20XV10 device mnemonic is used, the device
    parameters for the proper sub-mode are automatically
    selected according to the following:

A.  Input mode                  Mnemonic:  g20xv10i

    This mode is automatically chosen when the PLD source
    file has combinatorial output only.

    Input Only            Output Only           Input/Output
                           
     2, 3, 4,               14, 23               15, 16, 17,
     5, 6, 7,                                    18, 19, 20
     8, 9, 10,                                   21, 22
     11

     Pin 1 can be used both as a Synchronous Clock and an
     input. Pin 13 can be used both as a Common Output
     Enable (COE) and an input.

B.  Feedback mode               Mnemonic:  g20xv10f

    This mode is automatically chosen when the PLD source
    file has registered output.

    Input Only            Output Only           Input/Output
                           
     2, 3, 4,                                    14, 15, 16,
     5, 6, 7,                                    17, 18, 19,
     8, 9, 10,                                   20, 21, 22,
     11                                          23

    Pin 1 is the Synchronous Clock
    Pin 13 is the Common Output Enable (COE)
%%
%G22V10
G22V10 Architecture
Mnemonic: G22V10              Mnemonic: DIP
Pin Count: 24             Total Product Terms:  132
Extensions: OE D AR SP
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
LATTICE                       GAL22V10(UES)
LATTICE                       GAL22V10B
NATIONAL                      GAL22V10
_____________________________________________________________
Clock Pin(s): 1               Common OE(s):
VCC(s): 24                    GND(s): 12
Input Only: 1  2  3  4  5  6  7  8  9  10  11  13
Output Only:
Input/Output: 14  15  16  17  18  19  20  21  22  23
%%
%G22V10lcc
G22V10lcc Architecture
Mnemonic: G22V10lcc           Mnemonic: PLCC
Pin Count: 28             Total Product Terms:  132
Extensions: OE D AR SP
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
LATTICE                       GAL22V10(UES)
LATTICE                       GAL22V10B
NATIONAL                      GAL22V10
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
%%
%G22V10I
G22V10I Architecture
Mnemonic: G22V10I             Mnemonic: DIP/PLCC
Pin Count:28              Total Product Terms: 132
Extensions: OE D AR SP
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
LATTICE                       ispGAL22V10
_____________________________________________________________
Clock Pin(s): 8  9           Common OE(s):
VCC(s):  7                   GND(s): 21
Input Only:  10  11  12  13  14  16  17  18  19  20  22  23
Output Only:  1
Input/Output:  2  3  4  5  6  24  25  26  27  28
_____________________________________________________________
%%
%G24V10
G24V10 Architecture
Mnemonic: G24V10              Mnemonic: DIP/PLCC
Pin Count: 28             Total Product Terms:  80
Extensions: OE D
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       PALCE24V10H
_____________________________________________________________
Clock Pin(s): 1               Common OE(s): 15
VCC(s): 7                     GND(s): 21
Input Only: 1  2  3  4  5  6  8  9  10  11  12  13  14  27
            28
Output Only:
Input/Output: 16  17  18  19  20  22  23  24  25  26
%%
%G26CV12
G26CV12 Architecture
Mnemonic: G26CV12             Mnemonic: DIP/PLCC
Pin Count: 28             Total Product Terms:  120
Extensions: OE D AR SP
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
LATTICE                       GAL26CV12
_____________________________________________________________
%%
%G6001
G6001 Architecture
Mnemonic: G6001               Mnemonic: DIP
Pin Count: 24             Total Product Terms:   75
Extensions: OE D DQ LQ INT IO IOD IOL AR CK CE
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
LATTICE                       GAL6001
NATIONAL                      GAL6001
SGS-THOM.                     GAL6001
_____________________________________________________________
Clock Pin(s): 1               Common OE(s):
VCC(s): 24                    GND(s): 12
Input Only: 1  2  3  4  5  6  7  8  9  10  11
Output Only: 14  15  16  17  18  19  20  21  22  23
Input/Output:
_____________________________________________________________
Device Notes:
1.  The output logic macrocell feedback paths can be
    selected as internal only, I/O only, or both, via the
    .INT and .IO extensions. If the feedback type is the
    same as the output (internal feedback for registered
    output), then a feedback extension is not required.
2.  The output logic macrocells can be treated as buried
    register or combinatorial nodes, allowing the pins to be
    treated as inputs. The buried nodes must be defined in
    NODE or PINNODE statements and the input pins defined in
    PIN statements.
3.  All input pins can be configured as registered or
    latched inputs via the .DQ and .LQ extensions,
    respectively. Each input pin in a group must be treated
    in the same manner.
%%
%G6001lcc
G6001lcc Architecture
Mnemonic: G6001lcc            Mnemonic: PLCC
Pin Count: 28             Total Product Terms:   75
Extensions: OE D DQ LQ INT IO IOD IOL AR CK CE
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
LATTICE                       GAL6001
NATIONAL                      GAL6001
SGS-THOM.                     GAL6001
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
_____________________________________________________________
Device Notes:
1.  The output logic macrocell feedback paths can be
    selected as internal only, I/O only, or both, via the
    .INT and .IO extensions. If the feedback type is the
    same as the output (internal feedback for registered
    output), then a feedback extension is not required.
2.  The output logic macrocells can be treated as buried
    register or combinatorial nodes, allowing the pins to be
    treated as inputs. The buried nodes must be defined in
    NODE or PINNODE statements and the input pins defined in
    PIN statements.
3.  All input pins can be configured as registered or
    latched inputs via the .DQ and .LQ extensions,
    respectively. Each input pin in a group must be treated
    in the same manner.
%%
%G6002
G6002 Architecture
Mnemonic: G6002               Mnemonic: DIP
Pin Count: 24             Total Product Terms:   75
Extensions: OE D DQ LQ INT IO IOD IOL AR CK CE
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
LATTICE                       GAL6002B
_____________________________________________________________
Clock Pin(s): 1  13           Common OE(s):
VCC(s): 24                    GND(s): 12
Input Only: 1  2  3  4  5  6  7  8  9  10  11
Output Only: 14  15  16  17  18  19  20  21  22  23
Input/Output:
_____________________________________________________________
Device Notes:
1.  The output logic macrocell feedback paths can be
    selected as internal only, I/O only, or both, via the
    .INT and .IO extensions. If the feedback type is the
    same as the output (internal feedback for registered
    output), then a feedback extension is not required.
2.  The output logic macrocells can be treated as buried
    register or combinatorial nodes, allowing the pins to be
    treated as inputs. The buried nodes must be defined in
    NODE or PINNODE statements and the input pins defined in
    PIN statements.
3.  All input pins can be individually configured as
    straight through, registered or latched inputs.  Use the
    .DQ and .LQ extensions to get registered and latched
    inputs, respectively.
%%
%G6002lcc
G6002lcc Architecture
Mnemonic: G6002lcc            Mnemonic: PLCC
Pin Count: 28             Total Product Terms:   75
Extensions: OE D DQ LQ INT IO IOD IOL AR CK CE
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
LATTICE                       GAL6002B
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
_____________________________________________________________
Device Notes:
1.  The output logic macrocell feedback paths can be
    selected as internal only, I/O only, or both, via the
    .INT and .IO extensions. If the feedback type is the
    same as the output (internal feedback for registered
    output), then a feedback extension is not required.
2.  The output logic macrocells can be treated as buried
    register or combinatorial nodes, allowing the pins to be
    treated as inputs. The buried nodes must be defined in
    NODE or PINNODE statements and the input pins defined in
    PIN statements.
3.  All input pins can be individually configured as
    straight through, registered or latched inputs.  Use the
    .DQ and .LQ extensions to get registered and latched
    inputs, respectively.
%%
%GA2000
GA2000 Architecture
Mnemonic: GA2000                Mnemonic: DIP
Pin Count:                  Total Product Terms:
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
XILINX                        XC2064
XILINX                        XC2018
_____________________________________________________________
Device Notes:
1.  CUPL support for Xilinx devices must be purchased
    separately.  The support includes the Xilinx device
    library and ImproveX.
2.  This mnemonic is used to create an XNF file. Use the -zx
    flag with this mnemonic to generate an optimized XNF
    file. ( ImproveX is required to do this ).
%%
%GA3000
GA3000 Architecture
Mnemonic: GA3000                Mnemonic: DIP
Pin Count:                  Total Product Terms:
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
XILINX                        XC3020
XILINX                        XC3030
XILINX                        XC3042
XILINX                        XC3064
XILINX                        XC3090
_____________________________________________________________
Device Notes:
1.  CUPL support for Xilinx devices must be purchased
    separately.  The support includes the Xilinx device
    library and ImproveX.
2.  This mnemonic is used to create an XNF file. Use the -zx
    flag with this mnemonic to generate an optimized XNF
    file. ( ImproveX is required to do this ).
%%
%GA4000
GA4000 Architecture
Mnemonic: GA4000                Mnemonic: DIP
Pin Count:                  Total Product Terms:
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
XILINX                        XC4002A
XILINX                        XC4003/3A
XILINX                        XC4004A
XILINX                        XC4005/5A
XILINX                        XC4006
XILINX                        XC4008
XILINX                        XC4010
XILINX                        XC4013
XILINX                        XC4016
XILINX                        XC4020
_____________________________________________________________
Device Notes:
1.  CUPL support for Xilinx devices must be purchased
    separately.  The support includes the Xilinx device
    library and ImproveX.
2.  This mnemonic is used to create an XNF file. Use the -zx
    flag with this mnemonic to generate an optimized XNF
    file. ( ImproveX is required to do this ).
%%
%ISPL1016_60LH44
ISPL1016_60LH44 Architecture
Mnemonic: ISPL1016_60LH44      Mnemonic: PLCC
Pin Count: 44               Total Product Terms:
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
LATTICE                       ispLSI1016-60LH
_____________________________________________________________
Clock Pin(s):                Common OE(s):
VCC(s): 12  34               GND(s): 1  23
Input Only: 2  13  14  24  36
Output Only: 11  33  35
Input/Output: 3  4  5  6  7  8  9  10  15  16  17  18  19 20
              21  22  25  26  27  28  29  30  31  32  37  38
              39  40  41  42  43  44
Internal Nodes: 45 - 108
_____________________________________________________________
Device Notes:
1.  The pLSI fitter itself is not included with CUPL. This
    must be obtained separately from Lattice.
%%
%ISPL1016_60LJ44
ISPL1016_60LJ44 Architecture
Mnemonic: ISPL1016_60LJ44       Mnemonic: JLCC
Pin Count: 44               Total Product Terms:
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
LATTICE                       ispLSI1016-60LJ
_____________________________________________________________
Clock Pin(s):                Common OE(s):
VCC(s): 12  34               GND(s): 1  23
Input Only: 2  13  14  24  36
Output Only: 11  33  35
Input/Output: 3  4  5  6  7  8  9  10  15  16  17  18  19 20
              21  22  25  26  27  28  29  30  31  32  37  38
              39  40  41  42  43  44
_____________________________________________________________
Device Notes:
1.  The pLSI fitter itself is not included with CUPL. This
    must be obtained separately from Lattice.
%%
%ISPL1016_60LJ44I
ISPL1016_60LJ44I Architecture
Mnemonic: ISPL1016_60LJ44I      Mnemonic: JLCC
Pin Count: 44               Total Product Terms:
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
LATTICE                       ispLSI1016-60LJI
_____________________________________________________________
Clock Pin(s):                Common OE(s):
VCC(s): 12  34               GND(s): 1  23
Input Only: 2  13  14  24  36
Output Only: 11  33  35
Input/Output: 3  4  5  6  7  8  9  10  15  16  17  18  19 20
              21  22  25  26  27  28  29  30  31  32  37  38
              39  40  41  42  43  44
_____________________________________________________________
Device Notes:
1.  The pLSI fitter itself is not included with CUPL. This
    must be obtained separately from Lattice.
%%
%ISPL1016_60LJ44
ISPL1016_60LJ44 Architecture
Mnemonic: ISPL1016_60LJ44       Mnemonic: JLCC
Pin Count: 44               Total Product Terms:
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
LATTICE                       ispLSI1016-60LJ
_____________________________________________________________
Clock Pin(s):                Common OE(s):
VCC(s): 12  34               GND(s): 1  23
Input Only: 2  13  14  24  36
Output Only: 11  33  35
Input/Output: 3  4  5  6  7  8  9  10  15  16  17  18  19 20
              21  22  25  26  27  28  29  30  31  32  37  38
              39  40  41  42  43  44
_____________________________________________________________
Device Notes:
1.  The pLSI fitter itself is not included with CUPL. This
    must be obtained separately from Lattice.
%%
%ISPL1016_60LT44
ISPL1016_60LT44 Architecture
Mnemonic: ISPL1016_60LT44       Mnemonic: TQFP
Pin Count: 44               Total Product Terms:
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
LATTICE                       ispLSI1016-60LT
_____________________________________________________________
Clock Pin(s):                Common OE(s):
VCC(s): 6  28                GND(s): 17  39
Input Only: 8  18  27  30  40
Output Only: 5  27  29
Input/Output: 1  2  3  4  9  10  11  12  13  14  15  16  19
              20  21  22  23  24  25  26  31  32  33  34  35
              36  37  38  39  41  42  43  44
_____________________________________________________________
Device Notes:
1.  The pLSI fitter itself is not included with CUPL. This
    must be obtained separately from Lattice.
%%
%ISPL1016_80LJ44
ISPL1016_80LJ44 Architecture
Mnemonic: ISPL1016_80LJ44       Mnemonic: JLCC
Pin Count: 44               Total Product Terms:
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
LATTICE                       ispLSI1016-80LJ
_____________________________________________________________
Clock Pin(s):                Common OE(s):
VCC(s): 12  34               GND(s): 1  23
Input Only: 2  13  14  24  36
Output Only: 11  33  35
Input/Output: 3  4  5  6  7  8  9  10  15  16  17  18  19 20
              21  22  25  26  27  28  29  30  31  32  37  38
              39  40  41  42  43  44
_____________________________________________________________
Device Notes:
1.  The pLSI fitter itself is not included with CUPL. This
    must be obtained separately from Lattice.
%%
%ISPL1016_80LT44
ISPL1016_80LT44 Architecture
Mnemonic: ISPL1016_80LT44       Mnemonic: TQFP
Pin Count: 44               Total Product Terms:
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
LATTICE                       ispLSI1016-80LT
_____________________________________________________________
Clock Pin(s):                Common OE(s):
VCC(s): 6  28                GND(s): 17  39
Input Only: 8  18  27  30  40
Output Only: 5  27  29
Input/Output: 1  2  3  4  9  10  11  12  13  14  15  16  19
              20  21  22  23  24  25  26  31  32  33  34  35
              36  37  38  39  41  42  43  44
_____________________________________________________________
Device Notes:
1.  The pLSI fitter itself is not included with CUPL. This
    must be obtained separately from Lattice.
%%
%ISPL1016_90LJ44
ISPL1016_90LJ44 Architecture
Mnemonic: ISPL1016_90LJ44       Mnemonic: JLCC
Pin Count: 44               Total Product Terms:
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
LATTICE                       ispLSI1016-90LJ
_____________________________________________________________
Clock Pin(s):                Common OE(s):
VCC(s): 12  34               GND(s): 1  23
Input Only: 2  13  14  24  36
Output Only: 11  33  35
Input/Output: 3  4  5  6  7  8  9  10  15  16  17  18  19 20
              21  22  25  26  27  28  29  30  31  32  37  38
              39  40  41  42  43  44
_____________________________________________________________
Device Notes:
1.  The pLSI fitter itself is not included with CUPL. This
    must be obtained separately from Lattice.
%%
%ISPL1016_90LT44
ISPL1016_90LT44 Architecture
Mnemonic: ISPL1016_90LT44       Mnemonic: TQFP
Pin Count: 44               Total Product Terms:
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
LATTICE                       ispLSI1016-90LT
_____________________________________________________________
Clock Pin(s):                Common OE(s):
VCC(s): 6  28                GND(s): 17  39
Input Only: 8  18  27  30  40
Output Only: 5  27  29
Input/Output: 1  2  3  4  9  10  11  12  13  14  15  16  19
              20  21  22  23  24  25  26  31  32  33  34  35
              36  37  38  39  41  42  43  44
_____________________________________________________________
Device Notes:
1.  The pLSI fitter itself is not included with CUPL. This
    must be obtained separately from Lattice.
%%
%ISPL1016_110LJ44
ISPL1016_110LJ44 Architecture
Mnemonic: ISPL1016_110LJ44      Mnemonic: JLCC
Pin Count: 44               Total Product Terms:
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
LATTICE                       ispLSI1016-90LJ
_____________________________________________________________
Clock Pin(s):                Common OE(s):
VCC(s): 12  34               GND(s): 1  23
Input Only: 2  13  14  24  36
Output Only: 11  33  35
Input/Output: 3  4  5  6  7  8  9  10  15  16  17  18  19 20
              21  22  25  26  27  28  29  30  31  32  37  38
              39  40  41  42  43  44
_____________________________________________________________
Device Notes:
1.  The pLSI fitter itself is not included with CUPL. This
    must be obtained separately from Lattice.
%%
%ISPL1024_60LH68
ISPL1024_60LH68 Architecture
Mnemonic: ISPL1024_60LH68       Mnemonic: PLCC
Pin Count: 68               Total Product Terms:
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
LATTICE                       ispLSI1024-60LH
_____________________________________________________________
Clock Pin(s):                Common OE(s):
VCC(s): 17  36  53  68       GND(s): 1  18  35  52
Input Only: 2  15  19  20  21  34  49  55
Output Only: 16  50  51  54
Input/Output: 3  4  5  6  7  8  9  10  11  12  13  14  22  23
              24  25  26  27  28  29  30  31  32  33  37  38
              39  40  41  42  43  44  45  46  47  48  56  57
              58  59  60  61  62  63  64  65  66  67
_____________________________________________________________
Device Notes:
1.  The pLSI fitter itself is not included with CUPL. This
    must be obtained separately from Lattice.
%%
%ISPL1024_60LJ68
ISPL1024_60LJ68 Architecture
Mnemonic: ISPL1024_60LJ68       Mnemonic: JLCC
Pin Count: 68               Total Product Terms:
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
LATTICE                       ispLSI1024-60LJ
_____________________________________________________________
Clock Pin(s):                Common OE(s):
VCC(s): 17  36  53  68       GND(s): 1  18  35  52
Input Only: 2  15  19  20  21  34  49  55
Output Only: 16  50  51  54
Input/Output: 3  4  5  6  7  8  9  10  11  12  13  14  22  23
              24  25  26  27  28  29  30  31  32  33  37  38
              39  40  41  42  43  44  45  46  47  48  56  57
              58  59  60  61  62  63  64  65  66  67
_____________________________________________________________
Device Notes:
1.  The pLSI fitter itself is not included with CUPL. This
    must be obtained separately from Lattice.
%%
%ISPL1024_60LJ68I
ISPL1024_60LJ68I Architecture
Mnemonic: ISPL1024_60LJ68I      Mnemonic: JLCC
Pin Count: 68               Total Product Terms:
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
LATTICE                       ispLSI1024-60LJI
_____________________________________________________________
Clock Pin(s):                Common OE(s):
VCC(s): 17  36  53  68       GND(s): 1  18  35  52
Input Only: 2  15  19  20  21  34  49  55
Output Only: 16  50  51  54
Input/Output: 3  4  5  6  7  8  9  10  11  12  13  14  22  23
              24  25  26  27  28  29  30  31  32  33  37  38
              39  40  41  42  43  44  45  46  47  48  56  57
              58  59  60  61  62  63  64  65  66  67
_____________________________________________________________
Device Notes:
1.  The pLSI fitter itself is not included with CUPL. This
    must be obtained separately from Lattice.
%%
%ISPL1024_80LJ68
ISPL1024_80LJ68 Architecture
Mnemonic: ISPL1024_80LJ68       Mnemonic: JLCC
Pin Count: 68               Total Product Terms:
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
LATTICE                       ispLSI1024-80LJ
_____________________________________________________________
Clock Pin(s):                Common OE(s):
VCC(s): 17  36  53  68       GND(s): 1  18  35  52
Input Only: 2  15  19  20  21  34  49  55
Output Only: 16  50  51  54
Input/Output: 3  4  5  6  7  8  9  10  11  12  13  14  22  23
              24  25  26  27  28  29  30  31  32  33  37  38
              39  40  41  42  43  44  45  46  47  48  56  57
              58  59  60  61  62  63  64  65  66  67
_____________________________________________________________
Device Notes:
1.  The pLSI fitter itself is not included with CUPL. This
    must be obtained separately from Lattice.
%%
%ISPL1024_90LJ68
ISPL1024_90LJ68 Architecture
Mnemonic: ISPL1024_90LJ68       Mnemonic: JLCC
Pin Count: 68               Total Product Terms:
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
LATTICE                       ispLSI1024-90LJ
_____________________________________________________________
Clock Pin(s):                Common OE(s):
VCC(s): 17  36  53  68       GND(s): 1  18  35  52
Input Only: 2  15  19  20  21  34  49  55
Output Only: 16  50  51  54
Input/Output: 3  4  5  6  7  8  9  10  11  12  13  14  22  23
              24  25  26  27  28  29  30  31  32  33  37  38
              39  40  41  42  43  44  45  46  47  48  56  57
              58  59  60  61  62  63  64  65  66  67
_____________________________________________________________
Device Notes:
1.  The pLSI fitter itself is not included with CUPL. This
    must be obtained separately from Lattice.
%%
%ISPL1032_60LG84
ISPL1032_60LG84 Architecture
Mnemonic: ISPL1032_60LGJ84       Mnemonic: CPGA
Pin Count: 84               Total Product Terms:
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
LATTICE                       ispLSI1032-60LG
_____________________________________________________________
Clock Pin(s):                Common OE(s):
VCC(s):                      GND(s):
Input Only:
Output Only:
Input/Output:
_____________________________________________________________
Device Notes:
1.  The pLSI fitter itself is not included with CUPL. This
    must be obtained separately from Lattice.
%%
%ISPL1032_60LJ84
ISPL1032_60LJ84 Architecture
Mnemonic: ISPL1032_60LJ84       Mnemonic: PLCC
Pin Count: 84               Total Product Terms:
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
LATTICE                       ispLSI1032-60LJ
_____________________________________________________________
Clock Pin(s):                Common OE(s):
VCC(s): 21  65               GND(s): 1  22  43  64
Input Only: 2  19  23  24  25  42  44  61  67  84
Output Only: 20  62  63  66
Input/Output: 3  4  5  6  7  8  9  10  11  12  13  14  15  16
              17  18  26  27  28  29  30  31  32  33  34  35
              36  37  38  39  40  41  45  46  47  48  49  50
              51  52  53  54  55  56  57  58  59  60  68  69
              70  71  72  73  74  75  76  77  78  79  80  81
              82  83
_____________________________________________________________
Device Notes:
1.  The pLSI fitter itself is not included with CUPL. This
    must be obtained separately from Lattice.
%%
%ISPL1032_60LJ84I
ISPL1032_60LJ84I Architecture
Mnemonic: ISPL1032_60LJ84I      Mnemonic: PLCC
Pin Count: 84               Total Product Terms:
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
LATTICE                       ispLSI1032-60LJI
_____________________________________________________________
Clock Pin(s):                Common OE(s):
VCC(s): 21  65               GND(s): 1  22  43  64
Input Only: 2  19  23  24  25  42  44  61  67  84
Output Only: 20  62  63  66
Input/Output: 3  4  5  6  7  8  9  10  11  12  13  14  15  16
              17  18  26  27  28  29  30  31  32  33  34  35
              36  37  38  39  40  41  45  46  47  48  49  50
              51  52  53  54  55  56  57  58  59  60  68  69
              70  71  72  73  74  75  76  77  78  79  80  81
              82  83
_____________________________________________________________
Device Notes:
1.  The pLSI fitter itself is not included with CUPL. This
    must be obtained separately from Lattice.
%%
%ISPL1032_60LT100
ISPL1032_60LT100 Architecture
Mnemonic: ISPL1032_60LT100      Mnemonic: TQFP
Pin Count: 100              Total Product Terms:
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
LATTICE                       ispLSI1032-60LT
_____________________________________________________________
Clock Pin(s):                Common OE(s):
VCC(s):                      GND(s):
Input Only:
Output Only:
Input/Output:

_____________________________________________________________
Device Notes:
1.  The pLSI fitter itself is not included with CUPL. This
    must be obtained separately from Lattice.
%%
%ISPL1032_80LJ84
ISPL1032_80LJ84 Architecture
Mnemonic: ISPL1032_80LJ84       Mnemonic: PLCC
Pin Count: 84               Total Product Terms:
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
LATTICE                       ispLSI1032-80LJ
_____________________________________________________________
Clock Pin(s):                Common OE(s):
VCC(s): 21  65               GND(s): 1  22  43  64
Input Only: 2  19  23  24  25  42  44  61  67  84
Output Only: 20  62  63  66
Input/Output: 3  4  5  6  7  8  9  10  11  12  13  14  15  16
              17  18  26  27  28  29  30  31  32  33  34  35
              36  37  38  39  40  41  45  46  47  48  49  50
              51  52  53  54  55  56  57  58  59  60  68  69
              70  71  72  73  74  75  76  77  78  79  80  81
              82  83
_____________________________________________________________
Device Notes:
1.  The pLSI fitter itself is not included with CUPL. This
    must be obtained separately from Lattice.
%%
%ISPL1032_80LT100
ISPL1032_80LT100 Architecture
Mnemonic: ISPL1032_80LT100      Mnemonic: TQFP
Pin Count: 100              Total Product Terms:
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
LATTICE                       ispLSI1032-80LT
_____________________________________________________________
Clock Pin(s):                Common OE(s):
VCC(s):                      GND(s):
Input Only:
Output Only:
Input/Output:

_____________________________________________________________
Device Notes:
1.  The pLSI fitter itself is not included with CUPL. This
    must be obtained separately from Lattice.
%%
%ISPL1032_90LJ84
ISPL1032_90LJ84 Architecture
Mnemonic: ISPL1032_90LJ84       Mnemonic: PLCC
Pin Count: 84               Total Product Terms:
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
LATTICE                       ispLSI1032-90LJ
_____________________________________________________________
Clock Pin(s):                Common OE(s):
VCC(s): 21  65               GND(s): 1  22  43  64
Input Only: 2  19  23  24  25  42  44  61  67  84
Output Only: 20  62  63  66
Input/Output: 3  4  5  6  7  8  9  10  11  12  13  14  15  16
              17  18  26  27  28  29  30  31  32  33  34  35
              36  37  38  39  40  41  45  46  47  48  49  50
              51  52  53  54  55  56  57  58  59  60  68  69
              70  71  72  73  74  75  76  77  78  79  80  81
              82  83
_____________________________________________________________
Device Notes:
1.  The pLSI fitter itself is not included with CUPL. This
    must be obtained separately from Lattice.
%%
%ISPL1032_90LT100
ISPL1032_90LT100 Architecture
Mnemonic: ISPL1032_90LT100      Mnemonic: TQFP
Pin Count: 100              Total Product Terms:
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
LATTICE                       ispLSI1032-90LT
_____________________________________________________________
Clock Pin(s):                Common OE(s):
VCC(s):                      GND(s):
Input Only:
Output Only:
Input/Output:

_____________________________________________________________
Device Notes:
1.  The pLSI fitter itself is not included with CUPL. This
    must be obtained separately from Lattice.
%%
%ISPL1048_50LQ120
ISPL1048_50LQ120 Architecture
Mnemonic: ISPL1048_50LQ120      Mnemonic: PQFP
Pin Count: 120              Total Product Terms:
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
LATTICE                       ispLSI1048-50LQ
_____________________________________________________________
Clock Pin(s):                Common OE(s):
VCC(s): 15  45  77  107         GND(s): 16  46  76  106
Input Only: 13  17  18  19  44  47  48  73  79  104  105  108
Output Only: 14  74  75  78
Input/Output: 1  2  3  4  5  6  7  8  9  10  11  12   20  21
              22  23  24  25  26  27  28  29  30  31  32  33
              34  35  36  37  38  39  40  41  42  43  49  50
              51  52  53  54  55  56  57  58  59  60  61  62
              63  64  65  66  67  68  69  70  71  72  80  81
              82  83  84  85  86  87  88  89  90  91  92  93
              94  95  96  97  98  99  100  101 102  103  109
              110  111  112  113  114  115  116  117  118
              119  120
_____________________________________________________________
Device Notes:
1.  The pLSI fitter itself is not included with CUPL. This
    must be obtained separately from Lattice.
%%
%ISPL1048_50LQ120I
ISPL1048_50LQ120I Architecture
Mnemonic: ISPL1048_50LQ120I     Mnemonic: PQFP
Pin Count: 120              Total Product Terms:
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
LATTICE                       ispLSI1048-50LQI
_____________________________________________________________
Clock Pin(s):                Common OE(s):
VCC(s): 15  45  77  107         GND(s): 16  46  76  106
Input Only: 13  17  18  19  44  47  48  73  79  104  105  108
Output Only: 14  74  75  78
Input/Output: 1  2  3  4  5  6  7  8  9  10  11  12   20  21
              22  23  24  25  26  27  28  29  30  31  32  33
              34  35  36  37  38  39  40  41  42  43  49  50
              51  52  53  54  55  56  57  58  59  60  61  62
              63  64  65  66  67  68  69  70  71  72  80  81
              82  83  84  85  86  87  88  89  90  91  92  93
              94  95  96  97  98  99  100  101 102  103  109
              110  111  112  113  114  115  116  117  118
              119  120
_____________________________________________________________
Device Notes:
1.  The pLSI fitter itself is not included with CUPL. This
    must be obtained separately from Lattice.
%%
%ISPL1048_70LQ120
ISPL1048_70LQ120 Architecture
Mnemonic: ISPL1048_70LQ120      Mnemonic: PQFP
Pin Count: 120              Total Product Terms:
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
LATTICE                       ispLSI1048-70LQ
_____________________________________________________________
Clock Pin(s):                Common OE(s):
VCC(s): 15  45  77  107         GND(s): 16  46  76  106
Input Only: 13  17  18  19  44  47  48  73  79  104  105  108
Output Only: 14  74  75  78
Input/Output: 1  2  3  4  5  6  7  8  9  10  11  12   20  21
              22  23  24  25  26  27  28  29  30  31  32  33
              34  35  36  37  38  39  40  41  42  43  49  50
              51  52  53  54  55  56  57  58  59  60  61  62
              63  64  65  66  67  68  69  70  71  72  80  81
              82  83  84  85  86  87  88  89  90  91  92  93
              94  95  96  97  98  99  100  101 102  103  109
              110  111  112  113  114  115  116  117  118
              119  120
_____________________________________________________________
Device Notes:
1.  The pLSI fitter itself is not included with CUPL. This
    must be obtained separately from Lattice.
%%
%ISPL1048_80LQ120
ISPL1048_80LQ120 Architecture
Mnemonic: ISPL1048_80LQ120      Mnemonic: PQFP
Pin Count: 120              Total Product Terms:
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
LATTICE                       ispLSI1048-80LQ
_____________________________________________________________
Clock Pin(s):                Common OE(s):
VCC(s): 15  45  77  107         GND(s): 16  46  76  106
Input Only: 13  17  18  19  44  47  48  73  79  104  105  108
Output Only: 14  74  75  78
Input/Output: 1  2  3  4  5  6  7  8  9  10  11  12   20  21
              22  23  24  25  26  27  28  29  30  31  32  33
              34  35  36  37  38  39  40  41  42  43  49  50
              51  52  53  54  55  56  57  58  59  60  61  62
              63  64  65  66  67  68  69  70  71  72  80  81
              82  83  84  85  86  87  88  89  90  91  92  93
              94  95  96  97  98  99  100  101 102  103  109
              110  111  112  113  114  115  116  117  118
              119  120
_____________________________________________________________
Device Notes:
1.  The pLSI fitter itself is not included with CUPL. This
    must be obtained separately from Lattice.
%%
%ISPL1048C_50LG33
ISPL1048C_50LG33 Architecture
Mnemonic: ISPL1048C_50LG33      Mnemonic: CPGA
Pin Count: 133              Total Product Terms:
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
LATTICE                       ispLSI1048C-50LG
_____________________________________________________________
Clock Pin(s):                Common OE(s):
VCC(s):                         GND(s):
Input Only:
Output Only:
Input/Output:

_____________________________________________________________
Device Notes:
1.  The pLSI fitter itself is not included with CUPL. This
    must be obtained separately from Lattice.
%%
%ISPL1048C_50LQ28
ISPL1048C_50LQ28 Architecture
Mnemonic: ISPL1048C_50LQ28      Mnemonic: PQFP
Pin Count: 128              Total Product Terms:
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
LATTICE                       ispLSI1048C-50LQ
_____________________________________________________________
Clock Pin(s):                Common OE(s):
VCC(s):                         GND(s):
Input Only:
Output Only:
Input/Output:
_____________________________________________________________
Device Notes:
1.  The pLSI fitter itself is not included with CUPL. This
    must be obtained separately from Lattice.
%%
%ISPL1048C_50LQ8I
ISPL1048C_50LQ8I Architecture
Mnemonic: ISPL1048C_50LQ8I      Mnemonic: PQFP
Pin Count: 128              Total Product Terms:
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
LATTICE                       ispLSI1048C-50LQI
_____________________________________________________________
Clock Pin(s):                Common OE(s):
VCC(s):                         GND(s):
Input Only:
Output Only:
Input/Output:
_____________________________________________________________
Device Notes:
1.  The pLSI fitter itself is not included with CUPL. This
    must be obtained separately from Lattice.
%%
%ISPL1048C_70LQ28
ISPL1048C_70LQ28 Architecture
Mnemonic: ISPL1048C_70LQ28      Mnemonic: PQFP
Pin Count: 128              Total Product Terms:
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
LATTICE                       ispLSI1048C-70LQ
_____________________________________________________________
Clock Pin(s):                Common OE(s):
VCC(s):                         GND(s):
Input Only:
Output Only:
Input/Output:
_____________________________________________________________
Device Notes:
1.  The pLSI fitter itself is not included with CUPL. This
    must be obtained separately from Lattice.
%%
%ISPL2032_110LJ44
ISPL2032_110LJ44 Architecture
Mnemonic: ISPL2032_110LJ44      Mnemonic: PLCC
Pin Count: 44               Total Product Terms:
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
LATTICE                       ispLSI2032-110LJ
_____________________________________________________________
Clock Pin(s):                Common OE(s):
VCC(s): 12  34               GND(s): 1  23
Input Only: 2  13  14  24  36
Output Only: 11  33  35
Input/Output: 3  4  5  6  7  8  9  10  15  16  17  18  19 20
              21  22  25  26  27  28  29  30  31  32  37  38
              39  40  41  42  43  44
_____________________________________________________________
Device Notes:
1.  The pLSI fitter itself is not included with CUPL. This
    must be obtained separately from Lattice.
%%
%ISPL2032_110LT44
ISPL2032_110LT44 Architecture
Mnemonic: ISPL2032_110LT44      Mnemonic: TQFP
Pin Count: 44               Total Product Terms:
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
LATTICE                       ispLSI2032-110LT
_____________________________________________________________
Clock Pin(s):                Common OE(s):
VCC(s): 6  28                GND(s): 17  39
Input Only: 8  18  27  30  40
Output Only: 5  27  29
Input/Output: 1  2  3  4  9  10  11  12  13  14  15  16  19
              20  21  22  23  24  25  26  31  32  33  34  35
              36  37  38  39  41  42  43  44
_____________________________________________________________
Device Notes:
1.  The pLSI fitter itself is not included with CUPL. This
    must be obtained separately from Lattice.
%%
%ISPL2032_135LJ44
ISPL2032_135LJ44 Architecture
Mnemonic: ISPL2032_135LJ44      Mnemonic: PLCC
Pin Count: 44               Total Product Terms:
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
LATTICE                       ispLSI2032-135LJ
_____________________________________________________________
Clock Pin(s):                Common OE(s):
VCC(s): 12  34               GND(s): 1  23
Input Only: 2  13  14  24  36
Output Only: 11  33  35
Input/Output: 3  4  5  6  7  8  9  10  15  16  17  18  19 20
              21  22  25  26  27  28  29  30  31  32  37  38
              39  40  41  42  43  44
_____________________________________________________________
Device Notes:
1.  The pLSI fitter itself is not included with CUPL. This
    must be obtained separately from Lattice.
%%
%ISPL2032_135LT44
ISPL2032_135LT44 Architecture
Mnemonic: ISPL2032_135LT44      Mnemonic: TQFP
Pin Count: 44               Total Product Terms:
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
LATTICE                       ispLSI2032-135LT
_____________________________________________________________
Clock Pin(s):                Common OE(s):
VCC(s): 6  28                GND(s): 17  39
Input Only: 8  18  27  30  40
Output Only: 5  27  29
Input/Output: 1  2  3  4  9  10  11  12  13  14  15  16  19
              20  21  22  23  24  25  26  31  32  33  34  35
              36  37  38  39  41  42  43  44
_____________________________________________________________
Device Notes:
1.  The pLSI fitter itself is not included with CUPL. This
    must be obtained separately from Lattice.
%%
%ISPL2032_150LJ44
ISPL2032_150LJ44 Architecture
Mnemonic: ISPL2032_150LJ44      Mnemonic: PLCC
Pin Count: 44               Total Product Terms:
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
LATTICE                       ispLSI2032-150LJ
_____________________________________________________________
Clock Pin(s):                Common OE(s):
VCC(s): 12  34               GND(s): 1  23
Input Only: 2  13  14  24  36
Output Only: 11  33  35
Input/Output: 3  4  5  6  7  8  9  10  15  16  17  18  19 20
              21  22  25  26  27  28  29  30  31  32  37  38
              39  40  41  42  43  44
_____________________________________________________________
Device Notes:
1.  The pLSI fitter itself is not included with CUPL. This
    must be obtained separately from Lattice.
%%
%ISPL2032_150LT44
ISPL2032_150LT44 Architecture
Mnemonic: ISPL2032_150LT44      Mnemonic: TQFP
Pin Count: 44               Total Product Terms:
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
LATTICE                       ispLSI2032-150LT
_____________________________________________________________
Clock Pin(s):                Common OE(s):
VCC(s): 6  28                GND(s): 17  39
Input Only: 8  18  27  30  40
Output Only: 5  27  29
Input/Output: 1  2  3  4  9  10  11  12  13  14  15  16  19
              20  21  22  23  24  25  26  31  32  33  34  35
              36  37  38  39  41  42  43  44
_____________________________________________________________
Device Notes:
1.  The pLSI fitter itself is not included with CUPL. This
    must be obtained separately from Lattice.
%%
%ISPL2032_80LJ44
ISPL2032_80LJ44 Architecture
Mnemonic: ISPL2032_80LJ44      Mnemonic: PLCC
Pin Count: 44               Total Product Terms:
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
LATTICE                       ispLSI2032-80LJ
_____________________________________________________________
Clock Pin(s):                Common OE(s):
VCC(s): 12  34               GND(s): 1  23
Input Only: 2  13  14  24  36
Output Only: 11  33  35
Input/Output: 3  4  5  6  7  8  9  10  15  16  17  18  19 20
              21  22  25  26  27  28  29  30  31  32  37  38
              39  40  41  42  43  44
_____________________________________________________________
Device Notes:
1.  The pLSI fitter itself is not included with CUPL. This
    must be obtained separately from Lattice.
%%
%ISPL2032_80LT44
ISPL2032_80LT44 Architecture
Mnemonic: ISPL2032_80LT44      Mnemonic: TQFP
Pin Count: 44               Total Product Terms:
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
LATTICE                       ispLSI2032-80LT
_____________________________________________________________
Clock Pin(s):                Common OE(s):
VCC(s): 6  28                GND(s): 17  39
Input Only: 8  18  27  30  40
Output Only: 5  27  29
Input/Output: 1  2  3  4  9  10  11  12  13  14  15  16  19
              20  21  22  23  24  25  26  31  32  33  34  35
              36  37  38  39  41  42  43  44
_____________________________________________________________
Device Notes:
1.  The pLSI fitter itself is not included with CUPL. This
    must be obtained separately from Lattice.
%%
%ISPL2064_100LJ84
ISPL2064_100LJ84 Architecture
Mnemonic: ISPL2064_100LJ84      Mnemonic: PLCC
Pin Count: 84               Total Product Terms:
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
LATTICE                       ispLSI2064-100LJ
_____________________________________________________________
Clock Pin(s):                Common OE(s):
VCC(s): 21  65               GND(s): 1  22  43  64
Input Only: 2  19  23  24  25  42  44  61  67  84
Output Only: 20  62  63  66
Input/Output: 3  4  5  6  7  8  9  10  11  12  13  14  15  16
              17  18  26  27  28  29  30  31  32  33  34  35
              36  37  38  39  40  41  45  46  47  48  49  50
              51  52  53  54  55  56  57  58  59  60  68  69
              70  71  72  73  74  75  76  77  78  79  80  81
              82  83
_____________________________________________________________
Device Notes:
1.  The pLSI fitter itself is not included with CUPL. This
    must be obtained separately from Lattice.
%%
%ISPL2064_10LT100
ISPL2064_10LT100 Architecture
Mnemonic: ISPL2064_10LT100      Mnemonic: TQFP
Pin Count: 100              Total Product Terms:
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
LATTICE                       ispLSI2064-100LT
_____________________________________________________________
Clock Pin(s):                Common OE(s):
VCC(s):                      GND(s):
Input Only:
Output Only:
Input/Output:

_____________________________________________________________
Device Notes:
1.  The pLSI fitter itself is not included with CUPL. This
    must be obtained separately from Lattice.
%%
%ISPL2064_125LJ84
ISPL2064_125LJ84 Architecture
Mnemonic: ISPL2064_125LJ84      Mnemonic: PLCC
Pin Count: 84               Total Product Terms:
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
LATTICE                       ispLSI2064-125LJ
_____________________________________________________________
Clock Pin(s):                Common OE(s):
VCC(s): 21  65               GND(s): 1  22  43  64
Input Only: 2  19  23  24  25  42  44  61  67  84
Output Only: 20  62  63  66
Input/Output: 3  4  5  6  7  8  9  10  11  12  13  14  15  16
              17  18  26  27  28  29  30  31  32  33  34  35
              36  37  38  39  40  41  45  46  47  48  49  50
              51  52  53  54  55  56  57  58  59  60  68  69
              70  71  72  73  74  75  76  77  78  79  80  81
              82  83
_____________________________________________________________
Device Notes:
1.  The pLSI fitter itself is not included with CUPL. This
    must be obtained separately from Lattice.
%%
%ISPL2064_12LT100
ISPL2064_12LT100 Architecture
Mnemonic: ISPL2064_12LT100      Mnemonic: TQFP
Pin Count: 100              Total Product Terms:
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
LATTICE                       ispLSI2064-125LT
_____________________________________________________________
Clock Pin(s):                Common OE(s):
VCC(s):                      GND(s):
Input Only:
Output Only:
Input/Output:

_____________________________________________________________
Device Notes:
1.  The pLSI fitter itself is not included with CUPL. This
    must be obtained separately from Lattice.
%%
%ISPL2064_80LJ84
ISPL2064_80LJ84 Architecture
Mnemonic: ISPL2064_80LJ84      Mnemonic: PLCC
Pin Count: 84               Total Product Terms:
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
LATTICE                       ispLSI2064-80LJ
_____________________________________________________________
Clock Pin(s):                Common OE(s):
VCC(s): 21  65               GND(s): 1  22  43  64
Input Only: 2  19  23  24  25  42  44  61  67  84
Output Only: 20  62  63  66
Input/Output: 3  4  5  6  7  8  9  10  11  12  13  14  15  16
              17  18  26  27  28  29  30  31  32  33  34  35
              36  37  38  39  40  41  45  46  47  48  49  50
              51  52  53  54  55  56  57  58  59  60  68  69
              70  71  72  73  74  75  76  77  78  79  80  81
              82  83
_____________________________________________________________
Device Notes:
1.  The pLSI fitter itself is not included with CUPL. This
    must be obtained separately from Lattice.
%%
%ISPL2064_80LT100
ISPL2064_80LT100 Architecture
Mnemonic: ISPL2064_80LT100      Mnemonic: TQFP
Pin Count: 100              Total Product Terms:
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
LATTICE                       ispLSI2064-80LT
_____________________________________________________________
Clock Pin(s):                Common OE(s):
VCC(s):                      GND(s):
Input Only:
Output Only:
Input/Output:

_____________________________________________________________
Device Notes:
1.  The pLSI fitter itself is not included with CUPL. This
    must be obtained separately from Lattice.
%%
%ISPL2096_10LQ128
ISPL2096_10LQ128 Architecture
Mnemonic: ISPL2096_10LQ128      Mnemonic: PQFP
Pin Count: 128              Total Product Terms:
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
LATTICE                       ispLSI2096-100LQ
_____________________________________________________________
Clock Pin(s):                Common OE(s):
VCC(s):                         GND(s):
Input Only:
Output Only:
Input/Output:
_____________________________________________________________
Device Notes:
1.  The pLSI fitter itself is not included with CUPL. This
    must be obtained separately from Lattice.
%%
%ISPL2096_120LQ128
ISPL2096_12LQ128 Architecture
Mnemonic: ISPL2096_12LQ128      Mnemonic: PQFP
Pin Count: 128              Total Product Terms:
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
LATTICE                       ispLSI2096-125LQ
_____________________________________________________________
Clock Pin(s):                Common OE(s):
VCC(s):                         GND(s):
Input Only:
Output Only:
Input/Output:
_____________________________________________________________
Device Notes:
1.  The pLSI fitter itself is not included with CUPL. This
    must be obtained separately from Lattice.
%%
%ISPL2096_80LQ128
ISPL2096_80LQ128 Architecture
Mnemonic: ISPL2096_80LQ128      Mnemonic: PQFP
Pin Count: 128              Total Product Terms:
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
LATTICE                       ispLSI2096-80LQ
_____________________________________________________________
Clock Pin(s):                Common OE(s):
VCC(s):                         GND(s):
Input Only:
Output Only:
Input/Output:
_____________________________________________________________
Device Notes:
1.  The pLSI fitter itself is not included with CUPL. This
    must be obtained separately from Lattice.
%%
%ISPL2128_10LM160
ISPL2128_10LM160 Architecture
Mnemonic: ISPL2128_10LM160      Mnemonic: MQUAD
Pin Count: 160              Total Product Terms:
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
LATTICE                       ispLSI2128-100LM
_____________________________________________________________
Clock Pin(s):                Common OE(s):
VCC(s):                         GND(s):
Input Only:
Output Only:
Input/Output:
_____________________________________________________________
Device Notes:
1.  The pLSI fitter itself is not included with CUPL. This
    must be obtained separately from Lattice.
%%
%ISPL2128_80LM160
ISPL2128_80LM160 Architecture
Mnemonic: ISPL2128_80LM160      Mnemonic: MQUAD
Pin Count: 160              Total Product Terms:
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
LATTICE                       ispLSI2128-80LM
_____________________________________________________________
Clock Pin(s):                Common OE(s):
VCC(s):                         GND(s):
Input Only:
Output Only:
Input/Output:
_____________________________________________________________
Device Notes:
1.  The pLSI fitter itself is not included with CUPL. This
    must be obtained separately from Lattice.
%%
%ISPL3256_50LG167
ISPL3256_50LG167 Architecture
Mnemonic: ISPL3256_50LG167      Mnemonic: CPGA
Pin Count: 167              Total Product Terms:
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
LATTICE                       ispLSI3256-50LG
_____________________________________________________________
Clock Pin(s):                Common OE(s):
VCC(s):                         GND(s):
Input Only:
Output Only:
Input/Output:
_____________________________________________________________
Device Notes:
1.  The pLSI fitter itself is not included with CUPL. This
    must be obtained separately from Lattice.
%%
%ISPL3256_50LM160
ISPL3256_50LM160 Architecture
Mnemonic: ISPL3256_50LM160      Mnemonic: MQUAD
Pin Count: 167              Total Product Terms:
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
LATTICE                       ispLSI3256-50LM
_____________________________________________________________
Clock Pin(s):                Common OE(s):
VCC(s):                         GND(s):
Input Only:
Output Only:
Input/Output:
_____________________________________________________________
Device Notes:
1.  The pLSI fitter itself is not included with CUPL. This
    must be obtained separately from Lattice.
%%
%ISPL3256_70LG167
ISPL3256_70LG167 Architecture
Mnemonic: ISPL3256_70LG167      Mnemonic: CPGA
Pin Count: 167              Total Product Terms:
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
LATTICE                       ispLSI3256-70LG
_____________________________________________________________
Clock Pin(s):                Common OE(s):
VCC(s):                         GND(s):
Input Only:
Output Only:
Input/Output:
_____________________________________________________________
Device Notes:
1.  The pLSI fitter itself is not included with CUPL. This
    must be obtained separately from Lattice.
%%
%ISPL3256_70LM160
ISPL3256_70LM160 Architecture
Mnemonic: ISPL3256_70LM160      Mnemonic: MQUAD
Pin Count: 167              Total Product Terms:
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
LATTICE                       ispLSI3256-70LM
_____________________________________________________________
Clock Pin(s):                Common OE(s):
VCC(s):                         GND(s):
Input Only:
Output Only:
Input/Output:
_____________________________________________________________
Device Notes:
1.  The pLSI fitter itself is not included with CUPL. This
    must be obtained separately from Lattice.
%%
%ISPLSI
ISPLSI Architecture
Mnemonic: ISPLSI                Mnemonic:
Pin Count:                  Total Product Terms:
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
_____________________________________________________________
Clock Pin(s):                Common OE(s):
VCC(s):                         GND(s):
Input Only:
Output Only:
Input/Output:
_____________________________________________________________
Device Notes:
1.  The pLSI fitter itself is not included with CUPL. This
    must be obtained separately from Lattice.
%%
%KUFX780_132
KUFX780_132 Architecture
Mnemonic: KUFX780_132           Mnemonic: DIP
Pin Count: 132              Total Product Terms: 1024
Extensions: D T IO INT CK CKMUX CE DFB TFB OE OEMUX LE LEMUX
            AP AR SP SR FFM
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
INTEL                         IFX780 (132 PIN)
_____________________________________________________________
Clock Pin(s): 52  118        Common OE(s):
VCC(s): 19  20  21  50  51   GND(s): 11  17  18  27  44  53
        85  86  87  116  117         59  77  83  84  93  110
                                     119  125
Input Only: 1  2  3  4  5  33  34  35  36  37  38  52  65
            66  67  68  69  70  71  99  100  101  102  103
            104  118  131  132
Output Only:
Input/Output: 6  7  8  9  10  12  13  14  15  16  22  23  24
              25  26  28  29  30  31  32  39  40  41  42  43
              45  46  47  48  49  54  55  56  57  58  60  61
              62  63  64  72  73  74  75  76  78  79  80  81
              82  88  89  90  91  92  94  95  96  97  98
              105  106  107  108  109  111  112  113  114
              115  120  121  122  123  124  126  127  128
              129  130
_____________________________________________________________
%%
%M16V8A
M16V8A Architecture
Mnemonic: M16V8A              Mnemonic: DIP
Pin Count: 20             Total Product Terms:   64
Extensions: OE D
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
MICRON                        MPLD16V8A/LA
_____________________________________________________________
Clock Pin(s): 1               Common OE(s): 11
VCC(s): 20                    GND(s): 10
Input Only: 2  3  4  5  6  7  8  9
Output Only:
Input/Output: 12  13  14  15  16  17  18  19
_____________________________________________________________
Device Notes:
1.  This device emulates three different PAL architectures
    with their flexible output macro configuration. When
    this device mnemonic is used, the device parameters for
    the proper sub-mode are automatically selected according
    to the following:

A.  Registered Mode             Mnemonic: M16V8AR
    This mode is automatically chosen when the PLD source
    file has registered output. In the registered mode,
    specifying an output enable term for a registered
    output pin is not flagged as an error by the compiler or
    simulator.

    Input only      Output only    Input/Output
    ----------      -----------    ------------
     2, 3, 4,                       12, 13, 14,
     5, 6, 7,                       15, 16, 17,
     8, 9                           18, 19

    Pin 1 = common clock     Pin 11 = common output enable

    In this mode, the output enable control for registered
    pins is common to pin 11.

B.  Complex Mode                Mnemonic: M16V8AC
    This mode is automatically chosen when the PLD source
    file has an output enable term for a non-registered pin
    and/or combinatorial feedback.

    Input only     Output only    Input/Output
    ----------     -----------    ------------
     1, 2, 3,         12, 19       13, 14, 15,
     4, 5, 6,                      16, 17, 18
     7, 8, 9,
     11

C.  Simple Mode (Default)       Mnemonic: M16V8AS
    If none of the above are met, the device type defaults
    to the small mode. In this mode, the Input/Output pins
    are configured as either Input Only or Output only
    (that is, no feedback can occur).


    Input only     Output only    Input/Output
    ----------     -----------    ------------
     1, 2, 3,        15, 16        12, 13, 14,
     4, 5, 6,                      17, 18, 19
     7, 8, 9,
     11

2.  Either the automatic selection mechanism or the device
    mnemonic for the specific sub-mode desired can be used.
%%
%MACH110
MACH110 Architecture
Mnemonic: MACH110             Mnemonic: PLCC
Pin Count: 44             Total Product Terms: 140
Extensions: D T AP AR CKMUX OE OEMUX INT IO
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       MACH110-15/20
_____________________________________________________________
Clock Pin(s): 13  35          Common OE(s):
VCC(s): 22  44                GND(s): 1  12  23  34
Input Only: 10  11  13  32  33  35
Output Only:
Input/Output: 2  3  4  5  6  7  8  9  14  15  16  17  18  19
              20  21  24  25  26  27  28  29  30  31  36  37
              38  39  40  41  42  43
_____________________________________________________________
Device Notes:
1.  Due to memory restrictions imposed by DOS, the
    MACH FITR may not execute from the menu.  Instead, use
    the command line syntax as the compiler initiation
    procedure.
%%
%MACH111
MACH111 Architecture
Mnemonic: MACH111             Mnemonic: PLCC
Pin Count: 44             Total Product Terms: 140
Extensions: D T AP AR CKMUX OE OEMUX INT IO
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       MACH111-15/20
_____________________________________________________________
Clock Pin(s): 13  35          Common OE(s):
VCC(s): 22  44                GND(s): 1  12  23  34
Input Only: 10  11  13  32  33  35
Output Only:
Input/Output: 2  3  4  5  6  7  8  9  14  15  16  17  18  19
              20  21  24  25  26  27  28  29  30  31  36  37
              38  39  40  41  42  43
_____________________________________________________________
Device Notes:
1.  Due to memory restrictions imposed by DOS, the
    MACH FITR may not execute from the menu.  Instead, use
    the command line syntax as the compiler initiation
    procedure.
%%
%MACH120
MACH120 Architecture
Mnemonic: MACH120             Mnemonic: PLCC
Pin Count: 68             Total Product Terms:
Extensions: D T AP AR CKMUX OE OEMUX INT IO
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       MACH120-15/20
_____________________________________________________________
Clock Pin(s): 15  16  49  50  Common OE(s):
VCC(s): 18  34  52  68        GND(s): 1  8  19  27  35  42
                                      53  61
Input Only: 15  16  17  20  49  50  51  54
Output Only:
Input/Output: 2  3  4  5  6  7  9  10  11  12  13  14  21
              22  23  24  25  26  28  29  30  31  32  33  36
              37  38  39  40  41  43  44  45  46  47  48  55
              56  57  58  59  60  62  63  64  65  66  67
_____________________________________________________________
Device Notes:
1.  Due to memory restrictions imposed by DOS, the
    MACH FITR may not execute from the menu.  Instead, use
    the command line syntax as the compiler initiation
    procedure.
%%
%MACH130
MACH130 Architecture
Mnemonic: MACH130             Mnemonic: PLCC
Pin Count: 84             Total Product Terms: 280
Extensions: D T AP AR CKMUX OE OEMUX INT IO
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       MACH130-15/20
_____________________________________________________________
Clock Pin(s): 20  23  62  65  Common OE(s):
VCC(s): 2  21  42  63  84     GND(s): 1  11  22  32  43  53
                                      64  74
Input Only: 20  23  41  62  65  83
Output Only:
Input/Output: 3  4  5  6  7  8  9  10  12  13  14  15  16
              17  18  19  24  25  26  27  28  29  30  31  33
              34  35  36  37  38  39  40  45  46  47  48  49
              50  51  52  54  55  56  57  58  59  60  61  66
              67  68  69  70  71  72  73  75  76  77  78  79
              80  81  82

Device Notes:
1.  Due to memory restrictions imposed by DOS, the
    MACH FITR may not execute from the menu.  Instead, use
    the command line syntax as the compiler initiation
    procedure.
%%
%MACH131
MACH131 Architecture
Mnemonic: MACH131             Mnemonic: PLCC
Pin Count: 84             Total Product Terms: 280
Extensions: D T AP AR CKMUX OE OEMUX INT IO
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       MACH131-15/20
_____________________________________________________________
Clock Pin(s): 20  23  62  65  Common OE(s):
VCC(s): 2  21  42  63  84     GND(s): 1  11  22  32  43  53
                                      64  74
Input Only: 20  23  41  62  65  83
Output Only:
Input/Output: 3  4  5  6  7  8  9  10  12  13  14  15  16
              17  18  19  24  25  26  27  28  29  30  31  33
              34  35  36  37  38  39  40  45  46  47  48  49
              50  51  52  54  55  56  57  58  59  60  61  66
              67  68  69  70  71  72  73  75  76  77  78  79
              80  81  82

Device Notes:
1.  Due to memory restrictions imposed by DOS, the
    MACH FITR may not execute from the menu.  Instead, use
    the command line syntax as the compiler initiation
    procedure.
%%
%MACH210
MACH210 Architecture
Mnemonic: MACH210             Mnemonic: PLCC
Pin Count: 44             Total Product Terms: 280
Extensions: D T L DQ LQ AP AR CKMUX LEMUX OE OEMUX INT IO
            IOD IOL IOCK IOAR IOAP
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       MACH210-15/20
_____________________________________________________________
Clock Pin(s): 13  35          Common OE(s):
VCC(s): 22  44                GND(s): 1  12  23  34
Input Only: 10  11  13  32  33  35
Output Only:
Input/Output: 2  3  4  5  6  7  8  9  14  15  16  17  18  19
              20  21  24  25  26  27  28  29  30  31  36  37
              38  39  40  41  42  43
_____________________________________________________________
Device Notes:
1.  Due to memory restrictions imposed by DOS, the
    MACH FITR may not execute from the menu.  Instead, use
    the command line syntax as the compiler initiation
    procedure.
%%
%MACH215
MACH215 Architecture
Mnemonic: MACH215             Mnemonic: PLCC
Pin Count:                Total Product Terms: 256
Extensions: D T L DQ LQ AP AR LE  CKMUX LEMUX OE INT IO
            IOD IOL IOCK
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       MACH215-15/20
_____________________________________________________________
Clock Pin(s): 13  35          Common OE(s):
VCC(s): 22  44                GND(s): 1  12  23  34
Input Only: 10  11  13  32  33  35
Output Only:
Input/Output: 2  3  4  5  6  7  8  9  14  15  16  17  18  19
              20  21  24  25  26  27  28  29  30  31  36  37
              38  39  40  41  42  43
_____________________________________________________________
Device Notes:
1.  Due to memory restrictions imposed by DOS, the
    MACH FITR may not execute from the menu.  Instead, use
    the command line syntax as the compiler initiation
    procedure.
%%
%MACH220
MACH220 Architecture
Mnemonic: MACH220             Mnemonic: PLCC
Pin Count: 68             Total Product Terms:
Extensions: D T L DQ LQ AP AR CKMUX LEMUX OE OEMUX INT IO
            IOD IOL IOCK IOAR IOAP
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       MACH220-15/20
_____________________________________________________________
Clock Pin(s): 15  16  49  50  Common OE(s):
VCC(s): 18  34  52  68        GND(s): 1  8  19  27  35  42
                                      53  61
Input Only: 15  16  17  20  49  50  51  54
Output Only:
Input/Output: 2  3  4  5  6  7  9  10  11  12  13  14  21
              22  23  24  25  26  28  29  30  31  32  33  36
              37  38  39  40  41  43  44  45  46  47  48  55
              56  57  58  59  60  62  63  64  65  66  67
_____________________________________________________________
Device Notes:
1.  Due to memory restrictions imposed by DOS, the
    MACH FITR may not execute from the menu.  Instead, use
    the command line syntax as the compiler initiation
    procedure.
%%
%MACH221
MACH221 Architecture
Mnemonic: MACH221             Mnemonic: PLCC
Pin Count: 68             Total Product Terms:
Extensions: D T L DQ LQ AP AR CKMUX LEMUX OE OEMUX INT IO
            IOD IOL IOCK IOAR IOAP
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       MACH221-15/20
_____________________________________________________________
Clock Pin(s): 15  16  49  50  Common OE(s):
VCC(s): 18  34  52  68        GND(s): 1  8  19  27  35  42
                                      53  61
Input Only: 15  16  17  20  49  50  51  54
Output Only:
Input/Output: 2  3  4  5  6  7  9  10  11  12  13  14  21
              22  23  24  25  26  28  29  30  31  32  33  36
              37  38  39  40  41  43  44  45  46  47  48  55
              56  57  58  59  60  62  63  64  65  66  67
_____________________________________________________________
Device Notes:
1.  Due to memory restrictions imposed by DOS, the
    MACH FITR may not execute from the menu.  Instead, use
    the command line syntax as the compiler initiation
    procedure.
%%
%MACH230
MACH230 Architecture
Mnemonic: MACH230             Mnemonic: PLCC
Pin Count: 84             Total Product Terms:
Extensions: D T L DQ LQ AP AR CKMUX LEMUX OE OEMUX INT IO
            IOD IOL IOCK IOAR IOAP
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       MACH230-15/20
_____________________________________________________________
Clock Pin(s): 20  23  62  65  Common OE(s):
VCC(s): 2  21  42  63  84     GND(s): 1  11  22  32  43  53
                                      64  74
Input Only: 20  23  41  62  65  83
Output Only:
Input/Output: 3  4  5  6  7  8  9  10  12  13  14  15  16
              17  18  19  24  25  26  27  28  29  30  31  33
              34  35  36  37  38  39  40  45  46  47  48  49
              50  51  52  54  55  56  57  58  59  60  61  66
              67  68  69  70  71  72  73  75  76  77  78  79
              80  81  82
_____________________________________________________________
Device Notes:
1.  Due to memory restrictions imposed by DOS, the
    MACH FITR may not execute from the menu.  Instead, use
    the command line syntax as the compiler initiation
    procedure.
%%
%MACH231
MACH231 Architecture
Mnemonic: MACH231             Mnemonic: PLCC
Pin Count: 84             Total Product Terms:
Extensions: D T L DQ LQ AP AR CKMUX LEMUX OE OEMUX INT IO
            IOD IOL IOCK IOAR IOAP
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       MACH231-15/20
_____________________________________________________________
Clock Pin(s): 20  23  62  65  Common OE(s):
VCC(s): 2  21  42  63  84     GND(s): 1  11  22  32  43  53
                                      64  74
Input Only: 20  23  41  62  65  83
Output Only:
Input/Output: 3  4  5  6  7  8  9  10  12  13  14  15  16
              17  18  19  24  25  26  27  28  29  30  31  33
              34  35  36  37  38  39  40  45  46  47  48  49
              50  51  52  54  55  56  57  58  59  60  61  66
              67  68  69  70  71  72  73  75  76  77  78  79
              80  81  82
_____________________________________________________________
Device Notes:
1.  Due to memory restrictions imposed by DOS, the
    MACH FITR may not execute from the menu.  Instead, use
    the command line syntax as the compiler initiation
    procedure.
%%
%MACH335
MACH335 Architecture
Mnemonic: MACH335             Mnemonic: TQFP
Pin Count: 144            Total Product Terms: 480
Extensions: D T L DQ LQ AP AR CK CKMUX LEMUX OE INT IO IOD
            IOL IOCK IOAR IOAP
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD                           MACH335
_____________________________________________________________
Clock Pin(s):                Common OE(s):
VCC(s):                      GND(s):
Input Only:
Output Only:
Input/Output:

_____________________________________________________________

Device Notes:
1.  Due to memory restrictions imposed by DOS, the
    MACH FITR may not execute from the menu.  Instead, use
    the command line syntax as the compiler initiation
    procedure.
%%
%MACH435
MACH435 Architecture
Mnemonic: MACH435             Mnemonic: PLCC
Pin Count: 84             Total Product Terms: 720
Extensions: D T L DQ LQ AP AR CK CKMUX LEMUX OE INT IO IOD
            IOL IOCK IOAR IOAP
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD                           MACH435
_____________________________________________________________
Clock Pin(s): 20  23  62  65 Common OE(s):
VCC(s): 2  21  42  63  74 84 GND(s):1  11 22  32  43  53  64
Input Only: 20  23  41  62  65  83
Output Only:
Input/Output: 3  4  5  6  7  8  9  10 12  13  14  15  16  17
              18  19  24  25  26  27  28  29  30  31  33  34
              35  36  37  38  39  40  45  46  47  48  49  50
              51  52  54  55  56  57  58  59  60  61  66  67
              68  69  70  71  72  73  75  76  77  78  79  80
              81  82
_____________________________________________________________

Device Notes:
1.  Due to memory restrictions imposed by DOS, the
    MACH FITR may not execute from the menu.  Instead, use
    the command line syntax as the compiler initiation
    procedure.
%%
%MACH445
MACH445 Architecture
Mnemonic: MACH445             Mnemonic: TQFP
Pin Count: 100            Total Product Terms: 720
Extensions: D T L DQ LQ AP AR CK CKMUX LEMUX OE INT IO IOD
            IOL IOCK IOAR IOAP
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD                           MACH435
_____________________________________________________________
Clock Pin(s):                Common OE(s):
VCC(s):                      GND(s):
Input Only:
Output Only:
Input/Output:

_____________________________________________________________

Device Notes:
1.  Due to memory restrictions imposed by DOS, the
    MACH FITR may not execute from the menu.  Instead, use
    the command line syntax as the compiler initiation
    procedure.
%%
%MACH465
MACH465 Architecture
Mnemonic: MACH465             Mnemonic: TQFP
Pin Count: 208            Total Product Terms: 720
Extensions: D T L DQ LQ AP AR CK CKMUX LEMUX OE INT IO IOD
            IOL IOCK IOAR IOAP
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD                           MACH465
_____________________________________________________________
Clock Pin(s):                Common OE(s):
VCC(s):                      GND(s):
Input Only:
Output Only:
Input/Output:

_____________________________________________________________

Device Notes:
1.  Due to memory restrictions imposed by DOS, the
    MACH FITR may not execute from the menu.  Instead, use
    the command line syntax as the compiler initiation
    procedure.
%%
%MAPL128
MAPL128 Architecture
Mnemonic: MAPL128             Mnemonic: DIP/PLCC
Pin Count: 28             Total Product Terms:  132
Extensions: OE DE CE J K AR IO OEMUX
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
NATIONAL                      MAPL128
_____________________________________________________________
Clock Pin(s): 1               Common OE(s): 24
VCC(s): 28                    GND(s): 14
Input Only: 2  3  4  5  6  24  25  26  27
Output Only: 12  13  15  16
Input/Output: 7  8  9  10  11  17  18  19  20  21  22  23
_____________________________________________________________
Device Notes:
1.  To simulate this device, National has created two
    programs called OPALSIM and OPALVIEW.  Refer to the
    MAPL Design Guide for further information.
%%
%MAPL144
MAPL144 Architecture
Mnemonic: MAPL144             Mnemonic: PLCC
Pin Count: 44             Total Product Terms:  132
Extensions: OE DE CE J K AR IO OEMUX
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
NATIONAL                      MAPL144
_____________________________________________________________
Clock Pin(s): 1               Common OE(s): 39
VCC(s): 15  16  37  38        GND(s): 8  9  30  31
Input Only: 2  3  4  5  6  40  41  42  43
Output Only: 7  10  11  12  20  21  22  23  33  34  35  36
Input/Output: 13  14  17  18  19  24  25  26  27  28  29  32
_____________________________________________________________
Device Notes:
1.  To simulate this device, National has created two
    programs called OPALSIM and OPALVIEW.  Refer to the
    MAPL Design Guide for further information.
%%
%MAPL244
MAPL244 Architecture
Mnemonic: MAPL244             Mnemonic: DIP
Pin Count: 44             Total Product Terms:  224
Extensions: OE DE CE J K AR IO OEMUX CK CKMUX
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
NATIONAL                      MAPL244
_____________________________________________________________
Clock Pin(s): 10  17  39      Common OE(s): 42
VCC(s): 15  16  37  38        GND(s): 8  9  30  31
Input Only:
Output Only:
Input/Output: 1  2  3  4  5  6  7  11  12  13  14  18  19
              20  21  22  23  24  25  26  27  28  29  32  33
              34  35  36  40  41  43  44
%%
%MAX5032
MAX5032 Architecture
Mnemonic: MAX5032             Mnemonic: DIP
Pin Count: 28             Total Product Terms:  320
Extensions: OE D AP AR CK IO INT CKMUX
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
ALTERA                        EPM5032
_____________________________________________________________
Clock Pin(s): 2               Common OE(s):
VCC(s): 7  22                 GND(s): 8  21
Input Only: 1  2  13  14  15  16  27  28
Output Only:
Input/Output: 3  4  5  6  9  10  11  12  17  18  19  20  23
              24  25  26
_____________________________________________________________
Device Notes:
1.  To program a MAX device, a POF file is needed instead of
    a JEDEC file.  When the -j flag is used, a POF file will
    be created for these devices.
%%
%NFX740_44
NFX740_44 Architecture
Mnemonic: NFX740_44             Mnemonic: PLCC
Pin Count: 44               Total Product Terms: 512
Extensions: D T IO INT CK CKMUX CE DFB TFB OE OEMUX LE LEMUX
            AP AR SP SR FFM
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
INTEL                         IFX740 (44 PIN)
_____________________________________________________________
Clock Pin(s): 13  35         Common OE(s):
VCC(s): 12  23  34           GND(s): 1  14  15  36  37
Input Only: 13  21  22  35  43  44
Output Only:
Input/Output: 2  3  4  5  6  7  8  9  10  11  16  17  18  19
              20  24  25  26  27  28  29  30  31  32  33  38
              39  40  41  42
_____________________________________________________________
%%
%NFX740_68
NFX740_68 Architecture
Mnemonic: NFX740_68             Mnemonic: PLCC
Pin Count: 68               Total Product Terms: 512
Extensions: D T IO INT CK CKMUX CE DFB TFB OE OEMUX LE LEMUX
            AP AR SP SR FFM
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
INTEL                         IFX740 (68 PIN)
_____________________________________________________________
Clock Pin(s): 19  53         Common OE(s):
VCC(s): 17  18  20  35  51   GND(s): 1  21  34  54  55  68
        52
Input Only: 2  3  4  15  16  36  37  38  49  50
Output Only:
Input/Output: 5  6  7  8  9  10  11  12  13  14  22  23  24
              25  26  27  28  29  30  31  39  40  41  42  43
              44  45  46  47  48  56  57  58  59  60  61  62
              63  64  65
_____________________________________________________________
%%
%NFX780_84
NFX780_84 Architecture
Mnemonic: NFX780_84             Mnemonic: PLCC
Pin Count: 84               Total Product Terms: 1024
Extensions: D T IO INT CK CKMUX CE DFB TFB OE OEMUX LE LEMUX
            AP AR SP SR FFM
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
INTEL                         IFX780 (84 PIN)
_____________________________________________________________
Clock Pin(s): 3  45          Common OE(s):
VCC(s): 2  24  25  26  44    GND(s): 4  17  23  29  38  46
        66  67  68                   59  65  71  80
Input Only: 3  10  11  45  52  53
Output Only:
Input/Output: 1  5  6  7  8  9  12  13  14  15  16  18  19
              20  21  22  27  28  30  31  32  33  34  35  36
              37  39  40  41  42  43  47  48  49  50  51  54
              55  56  57  58  60  61  62  63  64  69  70  72
              73  74  75  76  77  78  79  81  82  83  84
_____________________________________________________________
%%
%P1012C4
P1012C4 Architecture
Mnemonic: P1012C4             Mnemonic: DIP
Pin Count: 24             Total Product Terms:   32
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
NATIONAL                      PAL10012C4
NATIONAL                      PAL1012C4
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
%%
%P1016C4
P1016C4 Architecture
Mnemonic: P1016C4             Mnemonic: DIP
Pin Count: 28             Total Product Terms:   32
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
NATIONAL                      PAL10016C4
NATIONAL                      PAL1016C4
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
%%
%P1016ET6
P1016ET6 Architecture
Mnemonic: P1016ET6            Mnemonic: DIP
Pin Count: 24             Total Product Terms:   48
Extensions: L
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
TI                            TIEPAL10016ET6
TI                            TIEPAL10016TE6
TI                            TIEPAL10H16ET6
TI                            TIEPAL10H16TE6
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
%%
%P1016LD4
P1016LD4 Architecture
Mnemonic: P1016LD4            Mnemonic: DIP
Pin Count: 24             Total Product Terms:   64
Extensions: L
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
NATIONAL                      PAL10016LD4
NATIONAL                      PAL1016LD4
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
%%
%P1016LD4lcc
P1016LD4lcc Architecture
Mnemonic: P1016LD4lcc         Mnemonic: PLCC
Pin Count: 28             Total Product Terms:   64
Extensions: L
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
NATIONAL                      PAL10016LD4
NATIONAL                      PAL1016LD4
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
%%
%P1016LD8
P1016LD8 Architecture
Mnemonic: P1016LD8            Mnemonic: DIP
Pin Count: 24             Total Product Terms:   64
Extensions: L
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
NATIONAL                      PAL10016LD8
NATIONAL                      PAL1016LD8
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
%%
%P1016LD8lcc
P1016LD8lcc Architecture
Mnemonic: P1016LD8lcc         Mnemonic: PLCC
Pin Count: 28             Total Product Terms:   64
Extensions: L
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
NATIONAL                      PAL10016LD8
NATIONAL                      PAL1016LD8
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
%%
%P1016LM4
P1016LM4 Architecture
Mnemonic: P1016LM4            Mnemonic: DIP
Pin Count: 24             Total Product Terms:   32
Extensions: L
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
NATIONAL                      PAL10016LM4
NATIONAL                      PAL1016LM4
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
%%
%P1016P4
P1016P4 Architecture
Mnemonic: P1016P4             Mnemonic: DIP
Pin Count: 24             Total Product Terms:   32
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
NATIONAL                      PAL10016P4
NATIONAL                      PAL1016P4
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
%%
%P1016P8
P1016P8 Architecture
Mnemonic: P1016P8             Mnemonic: DIP
Pin Count: 24             Total Product Terms:   64
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
NATIONAL                      PAL10016P8
NATIONAL                      PAL1016P8
TI                            TIEPAL10016P8-6
TI                            TIEPAL10H16P8-6
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
%%
%P1016PE8
P1016PE8 Architecture
Mnemonic: P1016PE8            Mnemonic: DIP
Pin Count: 28             Total Product Terms:   64
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
NATIONAL                      PAL10016PE8
NATIONAL                      PAL1016PE8
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
%%
%P1016RD4
P1016RD4 Architecture
Mnemonic: P1016RD4            Mnemonic: DIP
Pin Count: 24             Total Product Terms:   64
Extensions: D
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
NATIONAL                      PAL10016RD4
NATIONAL                      PAL1016RD4
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
%%
%P1016RD4lcc
P1016RD4lcc Architecture
Mnemonic: P1016RD4lcc         Mnemonic: PLCC
Pin Count: 28             Total Product Terms:   64
Extensions: D
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
NATIONAL                      PAL10016RD4
NATIONAL                      PAL1016RD4
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
%%
%P1016RD8
P1016RD8 Architecture
Mnemonic: P1016RD8            Mnemonic: DIP
Pin Count: 24             Total Product Terms:   64
Extensions: D
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
NATIONAL                      PAL10016RD8
NATIONAL                      PAL1016RD8
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
%%
%P1016RD8lcc
P1016RD8lcc Architecture
Mnemonic: P1016RD8lcc            Mnemonic: PLCC
Pin Count: 28             Total Product Terms:   64
Extensions: D
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
NATIONAL                      PAL10016RD8
NATIONAL                      PAL1016RD8
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
%%
%P1016RM4
P1016RM4 Architecture
Mnemonic: P1016RM4            Mnemonic: DIP
Pin Count: 24             Total Product Terms:   32
Extensions: D
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
NATIONAL                      PAL10016RM4
NATIONAL                      PAL1016RM4
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
%%
%P1020EG8
P1020EG8 Architecture
Mnemonic: P1020EG8            Mnemonic: DIP
Pin Count: 24             Total Product Terms:   80
Extensions: L OE AR AP
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       PAL10H/10020EG8
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s): 6  19  24             GND(s):
Latch Enable: 3               VEE(s): 12
Input Only: 1  2  3  9  10  11  13  14  15  16  22  23
Output Only:
Input/Output: 4  5  7  8  17  18  20  21
%%
%P1020EG8lcc
P1020EG8lcc Architecture
Mnemonic: P1020EG8lcc         Mnemonic: PLCC
Pin Count: 28             Total Product Terms:   80
Extensions: L OE AR AP
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       PAL10H/10020EG8
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Latch Enable:                 VEE(s):
Input Only:
Output Only:
Input/Output:
%%
%P1020EV8
P1020EV8 Architecture
Mnemonic: P1020EV8            Mnemonic: DIP
Pin Count: 24             Total Product Terms:   80
Extensions: D OE AR AP
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       PAL10H/10020EV8
PHILIPS                       10020EV8
PHILIPS                       10H20EV8
_____________________________________________________________
Clock Pin(s): 3               Common OE(s):
VCC(s): 6  19  24             GND(s):
VEE(s): 12
Input Only: 1  2  3  9  10  11  13  14  15  16  22  23
Output Only:
Input/Output: 4  5  7  8  17  18  20  21
%%
%P1020EV8lcc
P1020EV8lcc Architecture
Mnemonic: P1020EV8lcc         Mnemonic: PLCC
Pin Count: 28             Total Product Terms:   80
Extensions: D OE AR AP
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       PAL10H/10020EV8
PHILIPS                       10020EV8
PHILIPS                       10H20EV8
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
VEE(s):
Input Only:
Output Only:
Input/Output:
%%
%P1020G8
P1020G8 Architecture
Mnemonic: P1020G8             Mnemonic: DIP
Pin Count: 24             Total Product Terms:   32
Extensions: L
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       PAL10H20G8
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
%%
%P1020G8lcc
P1020G8lcc Architecture
Mnemonic: P1020G8lcc          Mnemonic: DIP
Pin Count: 28             Total Product Terms:   32
Extensions: L
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       PAL10H20G8
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
%%
%P1020P8
P1020P8 Architecture
Mnemonic: P1020P8             Mnemonic: DIP
Pin Count: 24             Total Product Terms:   32
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       PAL10H20P8
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
%%
%P1020P8lcc
P1020P8lcc Architecture
Mnemonic: P1020P8lcc          Mnemonic: PLCC
Pin Count: 28             Total Product Terms:   32
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       PAL10H20P8
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
%%
%P1020RP4
P1020RP4 Architecture
Mnemonic: P1020RP4            Mnemonic: DIP
Pin Count: 28             Total Product Terms:   32
Extensions: D
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
NATIONAL                      PAL10020RP4
NATIONAL                      PAL1020RP4
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
%%
%P10H8
P10H8 Architecture
Mnemonic: P10H8               Mnemonic: DIP
Pin Count: 20             Total Product Terms:   16
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       PAL10H8/-2
LATTICE                       RAL10H8
NATIONAL                      PAL10H8/16V8
NATIONAL                      PAL10H8/A/A2
SGS-THOM.                     RAL10H8
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s): 20                    GND(s): 10
Input Only: 1  2  3  4  5  6  7  8  9  11
Output Only: 12  13  14  15  16  17  18  19
Input/Output:
%%
%P10L8
P10L8 Architecture
Mnemonic: P10L8               Mnemonic: DIP
Pin Count: 20             Total Product Terms:   16
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       PAL10L8/-2
LATTICE                       RAL10L8
NATIONAL                      PAL10L8/16V8
NATIONAL                      PAL10L8/A/A2
SGS-THOM.                     RAL10L8
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s): 20                    GND(s): 10
Input Only: 1  2  3  4  5  6  7  8  9  11
Output Only: 12  13  14  15  16  17  18  19
Input/Output:
%%
%P10P8
P10P8 Architecture
Mnemonic: P10P8               Mnemonic: DIP
Pin Count: 20             Total Product Terms:   16
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
LATTICE                       RAL10P8
NATIONAL                      PAL10P8/16V8
SGS-THOM.                     RAL10P8
VLSI                          VP10P8
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
%%
%P10P8V
P10P8V Architecture
Mnemonic: P10P8V              Mnemonic: DIP
Pin Count: 20             Total Product Terms:   32
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
RICOH                         EPL10P8A
RICOH                         EPL10P8B
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
_____________________________________________________________
Device Notes:
1.  The output macrocell for this device is always
    configured for the OR path, utilizing double the product
    terms of a standard PAL. The default bypass path (lower
    power) and XOR path are not supported.
%%
%P12H6
P12H6 Architecture
Mnemonic: P12H6               Mnemonic: DIP
Pin Count: 20             Total Product Terms:   16
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       PAL12H6/-2
LATTICE                       RAL12H6
NATIONAL                      PAL12H6/16V8
NATIONAL                      PAL12H6/A/A2
SGS-THOM.                     RAL12H6
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s): 20                    GND(s): 10
Input Only: 1  2  3  4  5  6  7  8  9  11  12  19
Output Only: 13  14  15  16  17  18
Input/Output:
%%
%P12L10
P12L10 Architecture
Mnemonic: P12L10              Mnemonic: DIP
Pin Count: 24             Total Product Terms:   20
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       PAL12L10
CYPRESS                       PALC12L10
NATIONAL                      PAL12L10
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s): 24                    GND(s): 12
Input Only: 1  2  3  4  5  6  7  8  9  10  11  13
Output Only: 14  15  16  17  18  19  20  21  22  23
Input/Output:
%%
%P12L10lcc
P12L10lcc Architecture
Mnemonic: P12L10lcc           Mnemonic: PLCC
Pin Count: 28             Total Product Terms:   20
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       PAL12L10
CYPRESS                       PALC12L10
NATIONAL                      PAL12L10
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
%%
%P12L6
P12L6 Architecture
Mnemonic: P12L6               Mnemonic: DIP
Pin Count: 20             Total Product Terms:   16
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       PAL12L6/-2
LATTICE                       RAL12L6
NATIONAL                      PAL12L6/16V8
NATIONAL                      PAL12L6/A/A2
SGS-THOM.                     RAL12L6
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s): 20                    GND(s): 10
Input Only: 1  2  3  4  5  6  7  8  9  11  12  19
Output Only: 13  14  15  16  17  18
Input/Output:
%%
%P12P10
P12P10 Architecture
Mnemonic: P12P10              Mnemonic: DIP
Pin Count: 24             Total Product Terms:   20
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       PAL12P10
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s): 24                    GND(s): 12
Input Only: 1  2  3  4  5  6  7  8  9  10  11  13
Output Only: 14  15  16  17  18  19  20  21  22  23
Input/Output:
%%
%P12P10lcc
P12P10lcc Architecture
Mnemonic: P12P10lcc           Mnemonic: PLCC
Pin Count: 28             Total Product Terms:   20
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       PAL12P10
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s): 24                    GND(s): 12
Input Only: 1  2  3  4  5  6  7  8  9  10  11  13
Output Only: 14  15  16  17  18  19  20  21  22  23
Input/Output:
%%
%P12P6
P12P6 Architecture
Mnemonic: P12P6               Mnemonic: DIP
Pin Count: 20             Total Product Terms:   16
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
LATTICE                       RAL12P6
NATIONAL                      PAL12P6/16V8
SGS-THOM.                     RAL12P6
VLSI                          VP12P6
_____________________________________________________________
%%
%P12P6V
P12P6V Architecture
Mnemonic: P12P6V              Mnemonic: DIP
Pin Count: 20             Total Product Terms:   32
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
RICOH                         EPL12P6A
RICOH                         EPL12P6B
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
_____________________________________________________________
Device Notes:
1.  The output macrocell for this device is always
    configured for the OR path, utilizing double the product
    terms of a standard PAL. The default bypass path (lower
    power) and XOR path are not supported.
%%
%P14H4
P14H4 Architecture
Mnemonic: P14H4               Mnemonic: DIP
Pin Count: 20             Total Product Terms:   16
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       PAL14H4/-2
LATTICE                       RAL14H4
NATIONAL                      PAL14H4/16V8
NATIONAL                      PAL14H4/A/A2
SGS-THOM.                     RAL14H4
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s): 20                    GND(s): 10
Input Only: 1  2  3  4  5  6  7  8  9  11  12  13  18  19
Output Only: 14  15  16  17
Input/Output:
%%
%P14L4
P14L4 Architecture
Mnemonic: P14L4               Mnemonic: DIP
Pin Count: 20             Total Product Terms:   16
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       PAL14L4/-2
LATTICE                       RAL14L4
NATIONAL                      PAL14L4/16V8
NATIONAL                      PAL14L4/A/A2
SGS-THOM.                     RAL14L4
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s): 20                    GND(s): 10
Input Only: 1  2  3  4  5  6  7  8  9  11  12  13  18  19
Output Only: 14  15  16  17
Input/Output:
%%
%P14L8
P14L8 Architecture
Mnemonic: P14L8               Mnemonic: DIP
Pin Count: 24             Total Product Terms:   20
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       PAL14L8
CYPRESS                       PALC14L8
LATTICE                       RAL14L8
NATIONAL                      PAL14L8
NATIONAL                      PAL14L8/20V8
SGS-THOM.                     RAL14L8
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s): 24                    GND(s): 12
Input Only: 1  2  3  4  5  6  7  8  9  10  11  13  14  23
Output Only: 15  16  17  18  19  20  21  22
Input/Output:
%%
%P14L8lcc
P14L8lcc Architecture
Mnemonic: P14L8lcc            Mnemonic: PLCC
Pin Count: 28             Total Product Terms:   20
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       PAL14L8
CYPRESS                       PALC14L8
LATTICE                       RAL14L8
NATIONAL                      PAL14L8
NATIONAL                      PAL14L8/20V8
SGS-THOM.                     RAL14L8
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s): 24                    GND(s): 12
Input Only: 1  2  3  4  5  6  7  8  9  10  11  13  14  23
Output Only: 15  16  17  18  19  20  21  22
Input/Output:
%%
%P14P4
P14P4 Architecture
Mnemonic: P14P4               Mnemonic: DIP
Pin Count: 20             Total Product Terms:   16
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
LATTICE                       RAL14P4
NATIONAL                      PAL14P4/16V8
SGS-THOM.                     RAL14P4
VLSI                          VP14P4
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
%%
%P14P4V
P14P4V Architecture
Mnemonic: P14P4V              Mnemonic: DIP
Pin Count: 20             Total Product Terms:   32
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
RICOH                         EPL14P4A
RICOH                         EPL14P4B
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
_____________________________________________________________
Device Notes:
1.  The output macrocell for this device is always
    configured for the OR path, utilizing double the product
    terms of a standard PAL. The default bypass path (lower
    power) and XOR path are not supported.
%%
%P14P8
P14P8 Architecture
Mnemonic: P14P8               Mnemonic: DIP
Pin Count: 24             Total Product Terms:   20
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
LATTICE                       RAL14P8
NATIONAL                      PAL14P8/20V8
SGS-THOM.                     RAL14P8
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
%%
%P14P8lcc
P14P8lcc Architecture
Mnemonic: P14P8lcc            Mnemonic: PLCC
Pin Count: 28             Total Product Terms:   20
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
LATTICE                       RAL14P8
NATIONAL                      PAL14P8/20V8
SGS-THOM.                     RAL14P8
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
%%
%P14R21
P14R21 Architecture
Mnemonic: P14R21              Mnemonic: DIP
Pin Count: 24             Total Product Terms:   86
Extensions: D OE AP
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       PMS14R21
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
%%
%P16C1
P16C1 Architecture
Mnemonic: P16C1               Mnemonic: DIP
Pin Count: 20             Total Product Terms:   16
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       PAL16C1/-2
LATTICE                       RAL16C1
NATIONAL                      PAL16C1/A/A2
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s): 20                    GND(s): 10
Input Only: 1  2  3  4  5  6  7  8  9  11  12  13  14  17
            18  19
Output Only: 15  16
Input/Output:
%%
%P16H2
P16H2 Architecture
Mnemonic: P16H2               Mnemonic: DIP
Pin Count: 20             Total Product Terms:   16
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       PAL16H2/-2
LATTICE                       RAL16H2
NATIONAL                      PAL16H2/16V8
NATIONAL                      PAL16H2/A/A2
SGS-THOM.                     RAL16H2
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s): 20                    GND(s): 10
Input Only: 1  2  3  4  5  6  7  8  9  11  12  13  14  17
            18  19
Output Only: 15  16
Input/Output:
%%
%P16H8
P16H8 Architecture
Mnemonic: P16H8               Mnemonic: DIP
Pin Count: 20             Total Product Terms:   64
Extensions: OE
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       AMPAL16H8
HARRIS                        HPL16H8
LATTICE                       RAL16H8
NATIONAL                      PAL16H8/16V8
SGS-THOM.                     RAL16H8
TI                            TIBPAL16H8
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s): 20                    GND(s): 10
Input Only: 1  2  3  4  5  6  7  8  9  11
Output Only: 12  19
Input/Output: 13  14  15  16  17  18
%%
%P16HD8
P16HD8 Architecture
Mnemonic: P16HD8              Mnemonic: DIP
Pin Count: 20             Total Product Terms:   64
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       AMPAL16HD8
TI                            TIBPAL16HD8
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s): 20                    GND(s): 10
Input Only: 1  2  3  4  5  6  7  8  9  11
Output Only: 12  19
Input/Output: 13  14  15  16  17  18
%%
%P16L2
P16L2 Architecture
Mnemonic: P16L2               Mnemonic: DIP
Pin Count: 20             Total Product Terms:   16
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       PAL16L2/-2
LATTICE                       RAL16L2
NATIONAL                      PAL16L2/16V8
NATIONAL                      PAL16L2/A/A2
SGS-THOM.                     RAL16L2
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s): 20                    GND(s): 10
Input Only: 1  2  3  4  5  6  7  8  9  11  12  13  14  17
            18  19
Output Only: 15  16
Input/Output:
%%
%P16L6
P16L6 Architecture
Mnemonic: P16L6               Mnemonic: DIP
Pin Count: 24             Total Product Terms:   20
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       PAL16L6
CYPRESS                       PALC16L6
LATTICE                       RAL16L6
NATIONAL                      PAL16L6
NATIONAL                      PAL16L6/20V8
SGS-THOM.                     RAL16L6
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s): 24                    GND(s): 10
Input Only: 1  2  3  4  5  6  7  8  9  11  12  13  14  15
            22  23
Output Only: 16  17  18  19  20  21
Input/Output:
%%
%P16L6lcc
P16L6lcc Architecture
Mnemonic: P16L6lcc            Mnemonic: PLCC
Pin Count: 28             Total Product Terms:   20
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       PAL16L6
CYPRESS                       PALC16L6
LATTICE                       RAL16L6
NATIONAL                      PAL16L6
NATIONAL                      PAL16L6/20V8
SGS-THOM.                     RAL16L6
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
%%
%P16L8
P16L8 Architecture
Mnemonic: P16L8               Mnemonic: DIP
Pin Count: 20             Total Product Terms:   64
Extensions: OE
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       AMPAL16L8
AMD/MMI                       PAL16L8/A/A-2/A-4
AMD/MMI                       PAL16L8-5/7
AMD/MMI                       PAL16L8B
AMD/MMI                       PAL16L8B-2/B-4
AMD/MMI                       PAL16L8BP
AMD/MMI                       PAL16L8D
AMD/MMI                       PAL16L8H-10
AMD/MMI                       PAL16L8H-15
AMD/MMI                       PALC16L8Q
AMD/MMI                       PALC16L8Z
CYPRESS                       PAL16L8A
CYPRESS                       PAL16L8A-2
CYPRESS                       PAL16L8-5
CYPRESS                       PALC16L8
FAIRCHILD                     F16L8
HARRIS                        HPL16L8
HARRIS                        HPL16LC8
HARRIS                        HPL77209
LATTICE                       RAL16L8
NATIONAL                      PAL16L8/16V8
NATIONAL                      PAL16L8/A/A2/B/B2
NATIONAL                      PAL16L8D/-7
PHILIPS                       PLHS16L8A
PHILIPS                       PLHS16L8B
PHILIPS                       PLUS16L8D/-7
SAMSUNG                       CPL16L8
SAMSUNG                       CPL16L8L
SGS-THOM.                     RAL16L8
SPRAGUE                       SPL16LC8
TI                            PAL16L8A /-2
TI                            TIBPAL16L8-10
TI                            TIBPAL16L8-12/15/25
TI                            TIBPAL16L8-7
TI                            TIBPAL16O2
TI                            TICPAL16L8-55
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s): 20                    GND(s): 10
Input Only: 1  2  3  4  5  6  7  8  9  11
Output Only: 12  19
Input/Output: 13  14  15  16  17  18
%%
%P16L8ALCC
P16L8ALCC Architecture
Mnemonic: P16L8ALCC           PLCC Mnemonic: YES
Pin Count:                Total Product Terms:   64
Extensions: OE
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       PAL16L8-4
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s): 1 23                  GND(s): 6  9  11  13  15  17
                                      19  21
Input Only: 2  3  4  5  7  24  25  26  27  28
Output Only: 8  22
Input/Output: 10  12  14  16  18  20
%%
%P16LD8
P16LD8 Architecture
Mnemonic: P16LD8              Mnemonic: DIP
Pin Count: 20             Total Product Terms:   64
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       AMPAL16LD8
TI                            TIBPAL16LD8
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s): 20                    GND(s): 10
Input Only: 1  2  3  4  5  6  7  8  9  11
Output Only: 12  19
Input/Output: 13  14  15  16  17  18
%%
%P16N8
P16N8 Architecture
Mnemonic: P16N8               Mnemonic: DIP
Pin Count: 20             Total Product Terms:   16
Extensions: OE
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
PHILIPS                       PHD16N8
TI                            TIBPAD16N8-7.5
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
%%
%P16P2
P16P2 Architecture
Mnemonic: P16P2               Mnemonic: DIP
Pin Count: 20             Total Product Terms:   16
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
LATTICE                       RAL16P2
NATIONAL                      PAL16P2/16V8
SGS-THOM.                     RAL16P2
VLSI                          VP16P2
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
%%
%P16P2V
P16P2V Architecture
Mnemonic: P16P2V              Mnemonic: DIP
Pin Count: 20             Total Product Terms:   32
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
RICOH                         EPL16P2A
RICOH                         EPL16P2B
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
_____________________________________________________________
Device Notes:
1.  The output macrocell for this device is always
    configured for the OR path, utilizing double the product
    terms of a standard PAL. The default bypass path (lower
    power) and XOR path are not supported.
%%
%P16P4C
P16P4C Architecture
Mnemonic: P16P4C              Mnemonic: DIP
Pin Count: 24             Total Product Terms:   32
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
CYPRESS                       CY100E302
CYPRESS                       CY10E302
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s): 6  19  24             GND(s):
VEE(s): 12
Input Only: 1  2  3  9  10  11  13  14  15  16  22  23
Output Only: 5  7  18  20
Input/Output: 4  8  17  21
%%
%P16P4Clcc
P16P4Clcc Architecture
Mnemonic: P16P4Clcc           Mnemonic: PLCC
Pin Count: 28             Total Product Terms:   32
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
CYPRESS                       CY100E302
CYPRESS                       CY10E302
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s): 6  19  24             GND(s):
VEE(s): 12
Input Only: 1  2  3  9  10  11  13  14  15  16  22  23
Output Only: 5  7  18  20
Input/Output: 4  8  17  21
%%
%P16P6
P16P6 Architecture
Mnemonic: P16P6               Mnemonic: DIP
Pin Count: 24             Total Product Terms:   20
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
LATTICE                       RAL16P6
NATIONAL                      PAL16P6/20V8
SGS-THOM.                     RAL16P6
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
%%
%P16P6lcc
P16P6lcc Architecture
Mnemonic: P16P6lcc            Mnemonic: PLCC
Pin Count: 28             Total Product Terms:   20
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
LATTICE                       RAL16P6
NATIONAL                      PAL16P6/20V8
SGS-THOM.                     RAL16P6
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
%%
%P16P8
P16P8 Architecture
Mnemonic: P16P8               Mnemonic: DIP
Pin Count: 20             Total Product Terms:   64
Extensions: OE
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       PAL16P8A
AMD/MMI                       PAL16P8B
FAIRCHILD                     F16P8
LATTICE                       RAL16P8
NATIONAL                      PAL16P8
NATIONAL                      PAL16P8/16V8
SGS-THOM.                     RAL16P8
VLSI                          VP16P8
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s): 20                    GND(s): 10
Input Only: 1  2  3  4  5  6  7  8  9  11
Output Only: 12  19
Input/Output: 13  14  15  16  17  18
%%
%P16P8C
P16P8C Architecture
Mnemonic: P16P8C              PLCC Mnemonic: YES
Pin Count: 24             Total Product Terms:   32
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
CYPRESS                       CY100E301
CYPRESS                       CY10E301
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s): 6  19  24             GND(s):
VEE(s): 12
Input Only: 1  2  3  9  10  11  13  14  15  16  22  23
Output Only: 5  7  18  20
Input/Output: 4  8  17  21
%%
%P16P8H
P16P8H Architecture
Mnemonic: P16P8H              Mnemonic: DIP
Pin Count: 20             Total Product Terms:   64
Extensions: OE
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
HARRIS                        HPL16P8
HARRIS                        HPL77216
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s): 20                    GND(s): 10
Input Only: 1  2  3  4  5  6  7  8  9  11
Output Only: 12  19
Input/Output: 13  14  15  16  17  18
%%
%P16P8V
P16P8V Architecture
Mnemonic: P16P8V              Mnemonic: DIP
Pin Count: 20             Total Product Terms:   64
Extensions: OE
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
RICOH                         EPL16P8B
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
_____________________________________________________________
Device Notes:
1.  The output macrocell for this device is always
    configured for the default bypass path. The OR path
    (double product terms at the expense of an output pin)
    and XOR path are not supported.
%%
%P16R4
P16R4 Architecture
Mnemonic: P16R4               Mnemonic: DIP
Pin Count: 20             Total Product Terms:   64
Extensions: OE D
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       AMPAL16R4
AMD/MMI                       PAL16R4/A/A-2/A-4
AMD/MMI                       PAL16R4-5/7
AMD/MMI                       PAL16R4B
AMD/MMI                       PAL16R4B-2/B-4
AMD/MMI                       PAL16R4BP
AMD/MMI                       PAL16R4D
AMD/MMI                       PAL16R4H-10
AMD/MMI                       PAL16R4H-15
AMD/MMI                       PALC16R4Q
AMD/MMI                       PALC16R4Z
CYPRESS                       PAL16R4A
CYPRESS                       PAL16R4A-2
CYPRESS                       PAL16R4-5
CYPRESS                       PALC16R4
FAIRCHILD                     F16R4
HARRIS                        HPL16R4
LATTICE                       RAL16R4
NATIONAL                      PAL16R4/16V8
NATIONAL                      PAL16R4/A/A2/B/B2
NATIONAL                      PAL16R4D/-7
PHILIPS                       PLUS16R4D/-7
SAMSUNG                       CPL16R4
SAMSUNG                       CPL16R4L
SGS-THOM.                     RAL16R4
SPRAGUE                       SPL16RC4
TI                            PAL16R4A /-2
TI                            TIBPAL16R4-10
TI                            TIBPAL16R4-12/15/25
TI                            TIBPAL16R4-7
TI                            TICPAL16R4-55
_____________________________________________________________
Clock Pin(s): 1               Common OE(s): 11
VCC(s): 20                    GND(s): 10
Input Only: 2  3  4  5  6  7  8  9
Output Only: 14  15  16  17
Input/Output: 12  13  18  19
%%
%P16R4ALCC
P16R4ALCC Architecture
Mnemonic: P16R4ALCC           Mnemonic: PLCC
Pin Count:  28            Total Product Terms:   64
Extensions: D OE
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       PAL16R4-4
_____________________________________________________________
Clock Pin(s): 24              Common OE(s): 7
VCC(s): 1 23                  GND(s): 6  9  11  13  15  17
                                      19  21
Input Only: 2  3  4  5  25  26  27  28
Output Only: 12  14  16  18
Input/Output: 8  10  20  22
%%
%P16R6
P16R6 Architecture
Mnemonic: P16R6               Mnemonic: DIP
Pin Count: 20             Total Product Terms:   64
Extensions: OE D
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       AMPAL16R6
AMD/MMI                       PAL16R6/A/A-2/A-4
AMD/MMI                       PAL16R6-5/7
AMD/MMI                       PAL16R6B
AMD/MMI                       PAL16R6B-2/B-4
AMD/MMI                       PAL16R6BP
AMD/MMI                       PAL16R6D
AMD/MMI                       PAL16R6H-10
AMD/MMI                       PAL16R6H-15
AMD/MMI                       PALC16R6Q
AMD/MMI                       PALC16R6Z
CYPRESS                       PAL16R6A
CYPRESS                       PAL16R6A-2
CYPRESS                       PAL16R6-5
CYPRESS                       PALC16R6
FAIRCHILD                     F16R6
HARRIS                        HPL16R6
LATTICE                       RAL16R6
NATIONAL                      PAL16R6/16V8
NATIONAL                      PAL16R6/A/A2/B/B2
NATIONAL                      PAL16R6D/-7
PHILIPS                       PLUS16R6D/-7
SAMSUNG                       CPL16R6
SAMSUNG                       CPL16R6L
SGS-THOM.                     RAL16R6
SPRAGUE                       SPL16RC6
TI                            PAL16R6A /-2
TI                            TIBPAL16R6-10
TI                            TIBPAL16R6-12/15/25
TI                            TIBPAL16R6-7
TI                            TICPAL16R6-55
_____________________________________________________________
Clock Pin(s): 1               Common OE(s): 11
VCC(s): 20                    GND(s): 10
Input Only: 2  3  4  5  6  7  8  9
Output Only: 13  14  15  16  17  18
Input/Output: 12  19
%%
%P16R6ALCC
P16R6ALCC Architecture
Mnemonic: P16R6ALCC           Mnemonic: PLCC
Pin Count: 28             Total Product Terms:   64
Extensions: D OE
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       PAL16R6-4
_____________________________________________________________
Clock Pin(s): 24              Common OE(s): 7
VCC(s): 1  23                 GND(s): 6  9  11  13  15  17
                                      19  21
Input Only: 2  3  4  5  25  26  27  28
Output Only: 10  12  14  16  18  20
Input/Output: 8  22
%%
%P16R8
P16R8 Architecture
Mnemonic: P16R8               Mnemonic: DIP
Pin Count: 20             Total Product Terms:   64
Extensions: D
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       AMPAL16R8
AMD/MMI                       PAL16R8/A/A-2/A-4
AMD/MMI                       PAL16R8-5/7
AMD/MMI                       PAL16R8B
AMD/MMI                       PAL16R8B-2/B-4
AMD/MMI                       PAL16R8BP
AMD/MMI                       PAL16R8D
AMD/MMI                       PAL16R8H-10
AMD/MMI                       PAL16R8H-15
AMD/MMI                       PALC16R8Q
AMD/MMI                       PALC16R8Z
CYPRESS                       PAL16R8A
CYPRESS                       PAL16R8A-2
CYPRESS                       PAL16R8-5
CYPRESS                       PALC16R8
FAIRCHILD                     F16R8
HARRIS                        HPL16R8
LATTICE                       RAL16R8
NATIONAL                      PAL16R8/16V8
NATIONAL                      PAL16R8/A/A2/B/B2
NATIONAL                      PAL16R8D/-7
PHILIPS                       PLUS16R8D/-7
SAMSUNG                       CPL16R8
SAMSUNG                       CPL16R8L
SGS-THOM.                     RAL16R8
SPRAGUE                       SPL16RC8
TI                            PAL16R8A /-2
TI                            TIBPAL16R8-10
TI                            TIBPAL16R8-12/15/25
TI                            TIBPAL16R8-7
TI                            TICPAL16R8-55
_____________________________________________________________
Clock Pin(s): 1               Common OE(s):
VCC(s): 20                    GND(s): 10
Input Only: 2  3  4  5  6  7  8  9  11
Output Only: 12  13  14  15  16  17  18  19
Input/Output:
%%
%P16R8ALCC
P16R8ALCC Architecture
Mnemonic: P16R8ALCC           Mnemonic: PLCC
Pin Count: 28             Total Product Terms:   64
Extensions: D
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       PAL16R8-4
_____________________________________________________________
Clock Pin(s): 24              Common OE(s): 7
VCC(s): 1  23                 GND(s): 6  9  11  13  15  17
                                      19  21
Input Only: 2  3  4  5  25  26  27  28
Output Only: 8  10  12  14  16  18  20  22
Input/Output:
%%
%P16RA8
P16RA8 Architecture
Mnemonic: P16RA8              Mnemonic: DIP
Pin Count: 20             Total Product Terms:   64
Extensions: OE D AR AP CK IO
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       PAL16RA8
NATIONAL                      PAL16RA8
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
%%
%P16RP4
P16RP4 Architecture
Mnemonic: P16RP4              Mnemonic: DIP
Pin Count: 20             Total Product Terms:   64
Extensions: D OE
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       PAL16RP4A
FAIRCHILD                     F16RP4
HARRIS                        HPL16RC4
LATTICE                       RAL16RP4
NATIONAL                      PAL16RP4
NATIONAL                      PAL16RP4/16V8
SGS-THOM.                     RAL16RP4
VLSI                          VP16RP4
_____________________________________________________________
Clock Pin(s): 1  1            Common OE(s): 11  11
VCC(s): 20  20                GND(s): 10  10
Input Only: 2  2  3  3  4  4  5  5  6  6  7  7  8  8  9  9
Output Only: 14  14  15  15  16  16  17  17
Input/Output: 12  12  13  13  18  18  19  19
%%
%P16RP4V
P16RP4V Architecture
Mnemonic: P16RP4V             Mnemonic: DIP
Pin Count: 20             Total Product Terms:   64
Extensions: D OE
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
RICOH                         EPL16RP4B
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
_____________________________________________________________
Device Notes:
1.  The output macrocell for this device is always
    configured for the default bypass path. The OR path
    (double product terms at the expense of an output pin)
    and XOR path are not supported.
%%
%P16RP6
P16RP6 Architecture
Mnemonic: P16RP6              Mnemonic: DIP
Pin Count: 20             Total Product Terms:   64
Extensions: D OE
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       PAL16RP6A
FAIRCHILD                     F16RP6
HARRIS                        HPL16RC6
LATTICE                       RAL16RP6
NATIONAL                      PAL16RP6
NATIONAL                      PAL16RP6/16V8
SGS-THOM.                     RAL16RP6
VLSI                          VP16RP6
_____________________________________________________________
Clock Pin(s): 1  1            Common OE(s): 11  11
VCC(s): 20  20                GND(s): 10  10
Input Only: 2  2  3  3  4  4  5  5  6  6  7  7  8  8  9  9
Output Only: 13  13  14  14  15  15  16  16  17  17  18  18

Input/Output: 12  12  19  19
%%
%P16RP6V
P16RP6V Architecture
Mnemonic: P16RP6V             Mnemonic: DIP
Pin Count: 20             Total Product Terms:   64
Extensions: D OE
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
RICOH                         EPL16RP6B
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
_____________________________________________________________
Device Notes:
1.  The output macrocell for this device is always
    configured for the default bypass path. The OR path
    (double product terms at the expense of an output pin)
    and XOR path are not supported.
%%
%P16RP8
P16RP8 Architecture
Mnemonic: P16RP8              Mnemonic: DIP
Pin Count: 20             Total Product Terms:   64
Extensions: D
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       PAL16RP8A
FAIRCHILD                     F16RP8
HARRIS                        HPL16RC8
LATTICE                       RAL16RP8
NATIONAL                      PAL16RP8
NATIONAL                      PAL16RP8/16V8
SGS-THOM.                     RAL16RP8
VLSI                          VP16RP8
_____________________________________________________________
Clock Pin(s): 1  1            Common OE(s): 11  11
VCC(s): 20  20                GND(s): 10  10
Input Only: 2  2  3  3  4  4  5  5  6  6  7  7  8  8  9  9
Output Only: 12  12  13  13  14  14  15  15  16  16  17  17
              18  18  19  19

Input/Output:
%%
%P16RP8V
P16RP8V Architecture
Mnemonic: P16RP8V             Mnemonic: DIP
Pin Count: 20             Total Product Terms:   64
Extensions: D
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
RICOH                         EPL16RP8B
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
_____________________________________________________________
Device Notes:
1.  The output macrocell for this device is always
    configured for the default bypass path. The OR path
    (double product terms at the expense of an output pin)
    and XOR path are not supported.
%%
%P16RSP4
P16RSP4 Architecture
Mnemonic: P16RSP4             Mnemonic: DIP
Pin Count: 20             Total Product Terms:   64
Extensions: D OE
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
TI                            TICPAL16RSP4
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
%%
%P16RSP6
P16RSP6 Architecture
Mnemonic: P16RSP6             Mnemonic: DIP
Pin Count: 20             Total Product Terms:   64
Extensions: D OE
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
TI                            TICPAL16RSP6
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
%%
%P16RSP8
P16RSP8 Architecture
Mnemonic: P16RSP8             Mnemonic: DIP
Pin Count: 20             Total Product Terms:   64
Extensions: D OE
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
TI                            TICPAL16RSP8
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
%%
%P16SP8
P16SP8 Architecture
Mnemonic: P16SP8              Mnemonic: DIP
Pin Count: 20             Total Product Terms:   64
Extensions: OE
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
TI                            TICPAL16SP8
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
%%
%P18CV8
P18CV8 Architecture
Mnemonic: P18CV8              Mnemonic: DIP
Pin Count: 20             Total Product Terms:   74
Extensions: OE D AR SP INT DFB IO
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
GOULD                         PEEL18CV8
ICT                           PEEL18CV8
_____________________________________________________________
Clock Pin(s): 1               Common OE(s):
VCC(s): 20                    GND(s): 10
Input Only: 1  2  3  4  5  6  7  8  9  11
Output Only:
Input/Output: 12  13  14  15  16  17  18  19
_____________________________________________________________
Device Notes:
1.   The registered, internal combinatorial and I/O feedback
     paths can be selected by using the .DFB, .INT and .IO
     extensions respectively. If the feedback type is the
     same as the output (registered feedback for registered
     output), a feedback extension .IO is required.
%%
%P18G8
P18G8 Architecture
Mnemonic: P18G8               Mnemonic: DIP
Pin Count: 20             Total Product Terms:   72
Extensions: OE D IO DFB OEMUX
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
CYPRESS                       PLDC18G8
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
%%
%P18L4
P18L4 Architecture
Mnemonic: P18L4               Mnemonic: DIP
Pin Count: 24             Total Product Terms:   20
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       PAL18L4
CYPRESS                       PALC18L4
LATTICE                       RAL18L4
NATIONAL                      PAL18L4
NATIONAL                      PAL18L4/20V8
SGS-THOM.                     RAL18L4
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s): 24                    GND(s): 12
Input Only: 1  2  3  4  5  6  7  8  9  10  11  13  14  15
            16  21  22  23
Output Only: 17  18  19  20
Input/Output:
%%
%P18L4lcc
P18L4lcc Architecture
Mnemonic: P18L4lcc            Mnemonic: PLCC
Pin Count: 28             Total Product Terms:   20
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       PAL18L4
CYPRESS                       PALC18L4
LATTICE                       RAL18L4
NATIONAL                      PAL18L4
NATIONAL                      PAL18L4/20V8
SGS-THOM.                     RAL18L4
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s): 24                    GND(s): 12
Input Only: 1  2  3  4  5  6  7  8  9  10  11  13  14  15
            16  21  22  23
Output Only: 17  18  19  20
Input/Output:
%%
%P18N8
P18N8 Architecture
Mnemonic: P18N8               Mnemonic: DIP
Pin Count: 20             Total Product Terms:    8
Extensions: INT
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
TI                            TIBPAD18N8-6
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
%%
%P18P4
P18P4 Architecture
Mnemonic: P18P4               Mnemonic: DIP
Pin Count: 24             Total Product Terms:   20
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
LATTICE                       RAL18P4
NATIONAL                      PAL18P4/20V8
SGS-THOM.                     RAL18P4
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
%%
%P18P4lcc
P18P4lcc Architecture
Mnemonic: P18P4lcc            Mnemonic: PLCC
Pin Count: 28             Total Product Terms:   20
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
LATTICE                       RAL18P4
NATIONAL                      PAL18P4/20V8
SGS-THOM.                     RAL18P4
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
%%
%P18P8
P18P8 Architecture
Mnemonic: P18P8               Mnemonic: DIP
Pin Count: 20             Total Product Terms:   72
Extensions: OE
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       AMPAL18P8
PHILIPS                       PLHS18P8A
PHILIPS                       PLHS18P8B
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s): 20                    GND(s): 10
Input Only: 1  2  3  4  5  6  7  8  9  11
Output Only:
Input/Output: 12  13  14  15  16  17  18  19
%%
%P18U8
P18U8 Architecture
Mnemonic: P18U8               Mnemonic: DIP
Pin Count: 20             Total Product Terms:   72
Extensions: OEMUX OE D AR SP
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       PALC18U8
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
%%
%P18V8
P18V8 Architecture
Mnemonic: P18V8               Mnemonic: DIP
Pin Count: 20             Total Product Terms:   74
Extensions: OE D AR SP
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
TI                            TICPAL18V8
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
%%
%P19L8R
P19L8R Architecture
Mnemonic: P19L8R              Mnemonic: DIP
Pin Count: 24             Total Product Terms:   64
Extensions: OE DQ
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
TI                            TIBPALR19L8
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
%%
%P19L8Rlcc
P19L8Rlcc Architecture
Mnemonic: P19L8Rlcc           Mnemonic: PLCC
Pin Count: 28             Total Product Terms:   64
Extensions: OE DQ
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
TI                            TIBPALR19L8
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
%%
%P19L8T
P19L8T Architecture
Mnemonic: P19L8T              Mnemonic: DIP
Pin Count: 24             Total Product Terms:   64
Extensions: OE LQ
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
TI                            TIBPALT19L8
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
%%
%P19L8Tlcc
P19L8Tlcc Architecture
Mnemonic: P19L8Tlcc           Mnemonic: PLCC
Pin Count: 28             Total Product Terms:   64
Extensions: OE LQ
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
TI                            TIBPALT19L8
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
%%
%P19R4R
P19R4R Architecture
Mnemonic: P19R4R              Mnemonic: DIP
Pin Count: 24             Total Product Terms:   64
Extensions: OE DQ D
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
TI                            TIBPALR19R4
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
%%
%P19R4Rlcc
P19R4Rlcc Architecture
Mnemonic: P19R4Rlcc           Mnemonic: PLCC
Pin Count: 28             Total Product Terms:   64
Extensions: OE DQ D
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
TI                            TIBPALR19R4
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
%%
%P19R4T
P19R4T Architecture
Mnemonic: P19R4T              Mnemonic: DIP
Pin Count: 24             Total Product Terms:   64
Extensions: OE LQ D
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
TI                            TIBPALT19R4
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
%%
%P19R4Tlcc
P19R4Tlcc Architecture
Mnemonic: P19R4Tlcc           Mnemonic: PLCC
Pin Count: 28             Total Product Terms:   64
Extensions: OE LQ D
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
TI                            TIBPALT19R4
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
%%
%P19R6R
P19R6R Architecture
Mnemonic: P19R6R              Mnemonic: DIP
Pin Count: 24             Total Product Terms:   64
Extensions: OE DQ D
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
TI                            TIBPALR19R6
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
%%
%P19R6Rlcc
P19R6Rlcc Architecture
Mnemonic: P19R6Rlcc           Mnemonic: PLCC
Pin Count: 28             Total Product Terms:   64
Extensions: OE DQ D
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
TI                            TIBPALR19R6
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
%%
%P19R6T
P19R6T Architecture
Mnemonic: P19R6T              Mnemonic: DIP
Pin Count: 24             Total Product Terms:   64
Extensions: OE LQ D
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
TI                            TIBPALT19R6
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
%%
%P19R6Tlcc
P19R6Tlcc Architecture
Mnemonic: P19R6Tlcc           Mnemonic: PLCC
Pin Count: 28             Total Product Terms:   64
Extensions: OE LQ D
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
TI                            TIBPALT19R6
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
%%
%P19R8R
P19R8R Architecture
Mnemonic: P19R8R              Mnemonic: DIP
Pin Count: 24             Total Product Terms:   64
Extensions: OE DQ D
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
TI                            TIBPALR19R8
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
%%
%P19R8Rlcc
P19R8Rlcc Architecture
Mnemonic: P19R8Rlcc           Mnemonic: PLCC
Pin Count: 28             Total Product Terms:   64
Extensions: OE DQ D
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
TI                            TIBPALR19R8
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
%%
%P19R8T
P19R8T Architecture
Mnemonic: P19R8T              Mnemonic: DIP
Pin Count: 24             Total Product Terms:   64
Extensions: OE LQ D
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
TI                            TIBPALT19R8
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
%%
%P19R8Tlcc
P19R8Tlcc Architecture
Mnemonic: P19R8Tlcc           Mnemonic: PLCC
Pin Count: 28             Total Product Terms:   64
Extensions: OE LQ D
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
TI                            TIBPALT19R8
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
%%
%P20C1
P20C1 Architecture
Mnemonic: P20C1               Mnemonic: DIP
Pin Count: 24             Total Product Terms:   16
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       PAL20C1
NATIONAL                      PAL20C1
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s): 24                    GND(s): 12
Input Only: 1  2  3  4  5  6  7  8  9  10  11  13  14  15
            16  17  20  21  22  23

Output Only: 18  19
Input/Output:
%%
%P20C1lcc
P20C1lcc Architecture
Mnemonic: P20C1lcc            Mnemonic: PLCC
Pin Count: 28             Total Product Terms:   16
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       PAL20C1
NATIONAL                      PAL20C1
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s): 24                    GND(s): 12
Input Only: 1  2  3  4  5  6  7  8  9  10  11  13  14  15
            16  17  20  21  22  23

Output Only: 18  19
Input/Output:
%%
%P20CG10
P20CG10 Architecture
Mnemonic: P20CG10             Mnemonic: DIP
Pin Count: 24             Total Product Terms:   92
Extensions: OE D AR SP IO DFB INT
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
ICT                           PEEL20CG10
_____________________________________________________________
Clock Pin(s): 1               Common OE(s):
VCC(s): 24                    GND(s): 12
Input Only: 1  2  3  4  5  6  7  8  9  10  11  13
Output Only:
Input/Output: 14  15  16  17  18  19  20  21  22  23
%%
%P20CG10lcc
P20CG10lcc Architecture
Mnemonic: P20CG10lcc          Mnemonic: PLCC
Pin Count: 28             Total Product Terms:   92
Extensions: OE D AR SP IO DFB INT
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
ICT                           PEEL20CG10
_____________________________________________________________
Clock Pin(s): 1               Common OE(s):
VCC(s): 24                    GND(s): 12
Input Only: 1  2  3  4  5  6  7  8  9  10  11  13
Output Only:
Input/Output: 14  15  16  17  18  19  20  21  22  23
%%
%P20G10
P20G10 Architecture
Mnemonic: P20G10              Mnemonic: DIP
Pin Count: 24             Total Product Terms:   90
Extensions: D OE OEMUX
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
CYPRESS                       PLDC20G10
CYPRESS                       PLDC20G10B
CYPRESS                       PLDC20G10C
_____________________________________________________________
Clock Pin(s): 1               Common OE(s): 13
VCC(s): 24                    GND(s): 12
Input Only: 1  2  3  4  5  6  7  8  9  10  11  13
Output Only:
Input/Output: 14  15  16  17  18  19  20  21  22  23
%%
%P20G10lcc
P20G10lcc Architecture
Mnemonic: P20G10lcc           Mnemonic: PLCC
Pin Count: 28             Total Product Terms:   90
Extensions: D OE OEMUX
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
CYPRESS                       PLDC20G10
CYPRESS                       PLDC20G10B
CYPRESS                       PLDC20G10C
_____________________________________________________________
Clock Pin(s): 1               Common OE(s): 13
VCC(s): 24                    GND(s): 12
Input Only: 1  2  3  4  5  6  7  8  9  10  11  13
Output Only:
Input/Output: 14  15  16  17  18  19  20  21  22  23
%%
%P20L10
P20L10 Architecture
Mnemonic: P20L10              Mnemonic: DIP
Pin Count: 24             Total Product Terms:   40
Extensions: OE
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       AMPAL20L10
AMD/MMI                       PAL20L10
AMD/MMI                       PAL20L10A
CYPRESS                       PALC20L10
NATIONAL                      PAL20L10/A
SAMSUNG                       CPL20L10
SAMSUNG                       CPL20L10L
TI                            TIBPAL20L10
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s): 24                    GND(s): 12
Input Only: 1  2  3  4  5  6  7  8  9  10  11  13
Output Only: 14  23
Input/Output: 15  16  17  18  19  20  21  22
%%
%P20L10lcc
P20L10lcc Architecture
Mnemonic: P20L10lcc           Mnemonic: PLCC
Pin Count: 28             Total Product Terms:   40
Extensions: OE
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       AMPAL20L10
AMD/MMI                       PAL20L10
AMD/MMI                       PAL20L10A
CYPRESS                       PALC20L10
NATIONAL                      PAL20L10/A
SAMSUNG                       CPL20L10
SAMSUNG                       CPL20L10L
TI                            TIBPAL20L10
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
%%
%P20L2
P20L2 Architecture
Mnemonic: P20L2               Mnemonic: DIP
Pin Count: 24             Total Product Terms:   16
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       PAL20L2
CYPRESS                       PALC20L2
LATTICE                       RAL20L2
NATIONAL                      PAL20L2
NATIONAL                      PAL20L2/20V8
SGS-THOM.                     RAL20L2
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s): 24                    GND(s): 12
Input Only: 1  2  3  4  5  6  7  8  9  10  11  13  14  15
            16  17  20  21  22  23
Output Only: 18  19
Input/Output:
%%
%P20L2lcc
P20L2lcc Architecture
Mnemonic: P20L2lcc            Mnemonic: PLCC
Pin Count: 28             Total Product Terms:   16
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       PAL20L2
CYPRESS                       PALC20L2
LATTICE                       RAL20L2
NATIONAL                      PAL20L2
NATIONAL                      PAL20L2/20V8
SGS-THOM.                     RAL20L2
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
%%
%P20L8
P20L8 Architecture
Mnemonic: P20L8               Mnemonic: DIP
Pin Count: 24             Total Product Terms:   64
Extensions: OE
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       AMPAL20L8
AMD/MMI                       PAL20L8
AMD/MMI                       PAL20L8-5/7
AMD/MMI                       PAL20L8-10
AMD/MMI                       PAL20L8A/A-2
AMD/MMI                       PAL20L8B
AMD/MMI                       PAL20L8B-2
AMD/MMI                       PALC20L8Z
CYPRESS                       PALC20L8
LATTICE                       RAL20L8
NATIONAL                      PAL20L8/20V8
NATIONAL                      PAL20L8/A/B
NATIONAL                      PAL20L8D
PHILIPS                       PLUS20L8D/-7
SAMSUNG                       CPL20L8
SAMSUNG                       CPL20L8L
SGS-THOM.                     RAL20L8
SPRAGUE                       SPL20LC8
TI                            PAL20L8A
TI                            TIBPAL20L8-15/25
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s): 24                    GND(s): 12
Input Only: 1  2  3  4  5  6  7  8  9  10  11  13  14  23
Output Only: 15  22
Input/Output: 16  17  18  19  20  21
%%
%P20L8lcc
P20L8lcc Architecture
Mnemonic: P20L8lcc            Mnemonic: PLCC
Pin Count: 28             Total Product Terms:   64
Extensions: OE
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       AMPAL20L8
AMD/MMI                       PAL20L8
AMD/MMI                       PAL20L8-5/7
AMD/MMI                       PAL20L8-10
AMD/MMI                       PAL20L8A/A-2
AMD/MMI                       PAL20L8B
AMD/MMI                       PAL20L8B-2
AMD/MMI                       PALC20L8Z
CYPRESS                       PALC20L8
LATTICE                       RAL20L8
NATIONAL                      PAL20L8/20V8
NATIONAL                      PAL20L8/A/B
NATIONAL                      PAL20L8D
PHILIPS                       PLUS20L8D/-7
SAMSUNG                       CPL20L8
SAMSUNG                       CPL20L8L
SGS-THOM.                     RAL20L8
SPRAGUE                       SPL20LC8
TI                            PAL20L8A
TI                            TIBPAL20L8-15/25
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
%%
%P20P2
P20P2 Architecture
Mnemonic: P20P2               Mnemonic: DIP
Pin Count: 24             Total Product Terms:   16
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
LATTICE                       RAL20P2
NATIONAL                      PAL20P2/20V8
SGS-THOM.                     RAL20P2
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
%%
%P20P2lcc
P20P2lcc Architecture
Mnemonic: P20P2lcc            Mnemonic: PLCC
Pin Count: 28             Total Product Terms:   16
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
LATTICE                       RAL20P2
NATIONAL                      PAL20P2/20V8
SGS-THOM.                     RAL20P2
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
%%
%P20P4
P20P4 Architecture
Mnemonic: P20P4               Mnemonic: DIP
Pin Count: 24             Total Product Terms:   64
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
%%
%P20P6
P20P6 Architecture
Mnemonic: P20P6               Mnemonic: DIP
Pin Count: 24             Total Product Terms:   16
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
%%
%P20P8
P20P8 Architecture
Mnemonic: P20P8               Mnemonic: DIP
Pin Count: 24             Total Product Terms:   64
Extensions: OE
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
FAIRCHILD                     F20P8
LATTICE                       RAL20P8
NATIONAL                      PAL20P8/20V8
SGS-THOM.                     RAL20P8
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
%%
%P20P8lcc
P20P8lcc Architecture
Mnemonic: P20P8lcc            Mnemonic: PLCC
Pin Count: 28             Total Product Terms:   64
Extensions: OE
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
FAIRCHILD                     F20P8
LATTICE                       RAL20P8
NATIONAL                      PAL20P8/20V8
SGS-THOM.                     RAL20P8
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
%%
%P20R4
P20R4 Architecture
Mnemonic: P20R4               Mnemonic: DIP
Pin Count: 24             Total Product Terms:   64
Extensions: OE D
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       AMPAL20R4
AMD/MMI                       PAL20R4
AMD/MMI                       PAL20R4-5/7
AMD/MMI                       PAL20R4-10
AMD/MMI                       PAL20R4A/A-2
AMD/MMI                       PAL20R4B
AMD/MMI                       PAL20R4B-2
AMD/MMI                       PALC20R4Z
CYPRESS                       PALC20R4
LATTICE                       RAL20R4
NATIONAL                      PAL20R4/20V8
NATIONAL                      PAL20R4/A/B
NATIONAL                      PAL20R4D
PHILIPS                       PLUS20R4D/-7
SAMSUNG                       CPL20R4
SAMSUNG                       CPL20R4L
SGS-THOM.                     RAL20R4
TI                            PAL20R4A
TI                            TIBPAL20R4-15/25
_____________________________________________________________
Clock Pin(s): 1               Common OE(s): 13
VCC(s): 24                    GND(s): 12
Input Only: 2  3  4  5  6  7  8  9  10  11  14  23
Output Only: 17  18  19  20
Input/Output: 15  16  21  22
%%
%P20R4lcc
P20R4lcc Architecture
Mnemonic: P20R4lcc            Mnemonic: PLCC
Pin Count: 28             Total Product Terms:   64
Extensions: OE D
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       AMPAL20R4
AMD/MMI                       PAL20R4
AMD/MMI                       PAL20R4-5/7
AMD/MMI                       PAL20R4-10
AMD/MMI                       PAL20R4A/A-2
AMD/MMI                       PAL20R4B
AMD/MMI                       PAL20R4B-2
AMD/MMI                       PALC20R4Z
CYPRESS                       PALC20R4
LATTICE                       RAL20R4
NATIONAL                      PAL20R4/20V8
NATIONAL                      PAL20R4/A/B
NATIONAL                      PAL20R4D
PHILIPS                       PLUS20R4D/-7
SAMSUNG                       CPL20R4
SAMSUNG                       CPL20R4L
SGS-THOM.                     RAL20R4
TI                            PAL20R4A
TI                            TIBPAL20R4-15/25
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
%%
%P20R6
P20R6 Architecture
Mnemonic: P20R6               Mnemonic: DIP
Pin Count: 24             Total Product Terms:   64
Extensions: OE D
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       AMPAL20R6
AMD/MMI                       PAL20R6
AMD/MMI                       PAL20R6-5/7
AMD/MMI                       PAL20R6-10
AMD/MMI                       PAL20R6A/A-2
AMD/MMI                       PAL20R6B
AMD/MMI                       PAL20R6B-2
AMD/MMI                       PALC20R6Z
CYPRESS                       PALC20R6
LATTICE                       RAL20R6
NATIONAL                      PAL20R6/20V8
NATIONAL                      PAL20R6/A/B
NATIONAL                      PAL20R6D
PHILIPS                       PLUS20R6D/-7
SAMSUNG                       CPL20R6
SAMSUNG                       CPL20R6L
SGS-THOM.                     RAL20R6
TI                            PAL20R6A
TI                            TIBPAL20R6-15/25
_____________________________________________________________
Clock Pin(s): 1               Common OE(s): 13
VCC(s): 24                    GND(s): 12
Input Only: 2  3  4  5  6  7  8  9  10  11  14  23
Output Only: 16  17  18  19  20  21
Input/Output: 15  22
%%
%P20R6lcc
P20R6lcc Architecture
Mnemonic: P20R6lcc            Mnemonic: PLCC
Pin Count: 28             Total Product Terms:   64
Extensions: OE D
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       AMPAL20R6
AMD/MMI                       PAL20R6
AMD/MMI                       PAL20R6-5/7
AMD/MMI                       PAL20R6-10
AMD/MMI                       PAL20R6A/A-2
AMD/MMI                       PAL20R6B
AMD/MMI                       PAL20R6B-2
AMD/MMI                       PALC20R6Z
CYPRESS                       PALC20R6
LATTICE                       RAL20R6
NATIONAL                      PAL20R6/20V8
NATIONAL                      PAL20R6/A/B
NATIONAL                      PAL20R6D
PHILIPS                       PLUS20R6D/-7
SAMSUNG                       CPL20R6
SAMSUNG                       CPL20R6L
SGS-THOM.                     RAL20R6
TI                            PAL20R6A
TI                            TIBPAL20R6-15/25
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
%%
%P20R8
P20R8 Architecture
Mnemonic: P20R8               Mnemonic: DIP
Pin Count: 24             Total Product Terms:   64
Extensions: D
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       AMPAL20R8
AMD/MMI                       PAL20R8
AMD/MMI                       PAL20R8-5/7
AMD/MMI                       PAL20R8-10
AMD/MMI                       PAL20R8A/A-2
AMD/MMI                       PAL20R8B
AMD/MMI                       PAL20R8B-2
AMD/MMI                       PALC20R8Z
CYPRESS                       PALC20R8
LATTICE                       RAL20R8
NATIONAL                      PAL20R8/20V8
NATIONAL                      PAL20R8/A/B
NATIONAL                      PAL20R8D
PHILIPS                       PLUS20R8D/-7
SAMSUNG                       CPL20R8
SAMSUNG                       CPL20R8L
SGS-THOM.                     RAL20R8
TI                            PAL20R8A
TI                            TIBPAL20R8-15/25
_____________________________________________________________
Clock Pin(s): 1               Common OE(s): 13
VCC(s): 24                    GND(s): 12
Input Only: 2  3  4  5  6  7  8  9  10  11  14  23
Output Only: 15  16  17  18  19  20  21  22
Input/Output:
%%
%P20R8lcc
P20R8lcc Architecture
Mnemonic: P20R8lcc            Mnemonic: PLCC
Pin Count: 28             Total Product Terms:   64
Extensions: D
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       AMPAL20R8
AMD/MMI                       PAL20R8
AMD/MMI                       PAL20R8-5/7
AMD/MMI                       PAL20R8-10
AMD/MMI                       PAL20R8A/A-2
AMD/MMI                       PAL20R8B
AMD/MMI                       PAL20R8B-2
AMD/MMI                       PALC20R8Z
CYPRESS                       PALC20R8
LATTICE                       RAL20R8
NATIONAL                      PAL20R8/20V8
NATIONAL                      PAL20R8/A/B
NATIONAL                      PAL20R8D
PHILIPS                       PLUS20R8D/-7
SAMSUNG                       CPL20R8
SAMSUNG                       CPL20R8L
SGS-THOM.                     RAL20R8
TI                            PAL20R8A
TI                            TIBPAL20R8-15/25
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
%%
%P20RA10
P20RA10 Architecture
Mnemonic: P20RA10             Mnemonic: DIP
Pin Count: 24             Total Product Terms:   80
Extensions: OE D AR AP CK IO
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       PAL20RA10
AMD/MMI                       PALCE20RA10
CYPRESS                       PLDC20RA10
NATIONAL                      PAL20RA10
SEEQ                          20RA10Z
_____________________________________________________________
Clock Pin(s):                 Common OE(s): 13  13
VCC(s): 12  24  24            GND(s): 12
VEE(s): 1
Input Only: 2  3  4  5  6  7  8  9  10  11
Output Only:
Input/Output: 14  15  16  17  18  19  20  21  22  23
_____________________________________________________________
Device Notes:
1.  Combinatorial Output
    As with any other device that can have combinatorial
    output, an extension is not needed to define an output
    to be combinatorial. When an output is defined to be
    combinatorial, CUPL will automatically set the AP and AR
    to 'b'1 enabling the register to be bypassed.
2.  Registered Output
    The 20RA10 has only one feedback path, the I/O feedback.
    When using registered output normally the feedback would
    come from the register, but in this device the feedback
    comes from the pin. If the feedback is needed the IO
    extension must be added to the variable name to use the
    pin feedback path.  This follows the CUPL rules for when
    to use feedback extensions.
3.  Programmable Preset and Reset
    In each macrocell, two product lines are dedicated to
    asynchronous preset (AP) and asynchronous reset (AR).
    If the AP line is HIGH, the Q output of the register
    becomes a logic 1.  If the AR line is HIGH, the Q output
    of the register becomes a logic 0.  If both the AP and
    AR lines are HIGH, the flip-flop is bypassed and the
    output becomes combinatorial.  The operation of AP and
    AR overrides the asynchronous clock (CK).
4.  Three-State (OE) Outputs
    The 20RA10 has a product term dedicated to local output
    control (OE) and also a global output control pin.  The
    output is enabled if both the global output control pin
    is LOW and the local output control product term is
    HIGH.  If the global output control pin is HIGH, all
    outputs will be disabled.  If the local output control
    product term is LOW, then that output will be disabled.
5.  Non-JEDEC Pinouts
    The P20RA10 has three different pinout configurations for
    the LCC and PLCC devices. The JEDEC pinout is the only
    one selectable from the menu. If you want a different
    pinout configuration you must use the proper mnemonic in
    the DEVICE field of the source (.pld) file. The following
    table shows the mnemonic needed for each of the different
    pinout configurations:

            Pinout configuration            Mnemonic
            --------------------          ------------
                  JEDEC                    P20RA10LCC
                  Standard                 P20RA10SLCC
                  Military                 P20RA10MLCC
%%
%P20RA10lcc
P20RA10lcc Architecture
Mnemonic: P20RA10lcc          Mnemonic: PLCC
Pin Count: 28             Total Product Terms:   80
Extensions: OE D AR AP CK IO
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       PAL20RA10
AMD/MMI                       PALCE20RA10
CYPRESS                       PLDC20RA10
NATIONAL                      PAL20RA10
SEEQ                          20RA10Z
_____________________________________________________________
Clock Pin(s):                 Common OE(s): 13  13
VCC(s): 12  24  24            GND(s): 12
VEE(s): 1
Input Only: 2  3  4  5  6  7  8  9  10  11
Output Only:
Input/Output: 14  15  16  17  18  19  20  21  22  23
_____________________________________________________________
Device Notes:
1.  Combinatorial Output
    As with any other device that can have combinatorial
    output, an extension is not needed to define an output
    to be combinatorial. When an output is defined to be
    combinatorial, CUPL will automatically set the AP and AR
    to 'b'1 enabling the register to be bypassed.
2.  Registered Output
    The 20RA10 has only one feedback path, the I/O feedback.
    When using registered output normally the feedback would
    come from the register, but in this device the feedback
    comes from the pin. If the feedback is needed the IO
    extension must be added to the variable name to use the
    pin feedback path.  This follows the CUPL rules for when
    to use feedback extensions.
3.  Programmable Preset and Reset
    In each macrocell, two product lines are dedicated to
    asynchronous preset (AP) and asynchronous reset (AR).
    If the AP line is HIGH, the Q output of the register
    becomes a logic 1.  If the AR line is HIGH, the Q output
    of the register becomes a logic 0.  If both the AP and
    AR lines are HIGH, the flip-flop is bypassed and the
    output becomes combinatorial.  The operation of AP and
    AR overrides the asynchronous clock (CK).
4.  Three-State (OE) Outputs
    The 20RA10 has a product term dedicated to local output
    control (OE) and also a global output control pin.  The
    output is enabled if both the global output control pin
    is LOW and the local output control product term is
    HIGH.  If the global output control pin is HIGH, all
    outputs will be disabled.  If the local output control
    product term is LOW, then that output will be disabled.
5.  Non-JEDEC Pinouts
    The P20RA10 has three different pinout configurations for
    the LCC and PLCC devices. The JEDEC pinout is the only
    one selectable from the menu. If you want a different
    pinout configuration you must use the proper mnemonic in
    the DEVICE field of the source (.pld) file. The following
    table shows the mnemonic needed for each of the different
    pinout configurations:

            Pinout configuration            Mnemonic
            --------------------          ------------
                  JEDEC                    P20RA10LCC
                  Standard                 P20RA10SLCC
                  Military                 P20RA10MLCC
%%
%P20RP10A
P20RP10A Architecture
Mnemonic: P20RP10A            Mnemonic: DIP
Pin Count: 24             Total Product Terms:   80
Extensions: OE D
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       AMPAL20RP10
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
%%
%P20RP10Alcc
P20RP10Alcc Architecture
Mnemonic: P20RP10Alcc         Mnemonic: PLCC
Pin Count: 28             Total Product Terms:   80
Extensions: OE D
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       AMPAL20RP10
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
%%
%P20RP4
P20RP4 Architecture
Mnemonic: P20RP4              Mnemonic: DIP
Pin Count: 24             Total Product Terms:   64
Extensions: OE D
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
FAIRCHILD                     F20RP4
LATTICE                       RAL20RP4
NATIONAL                      PAL20RP4/20V8
SGS-THOM.                     RAL20RP4
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
%%
%P20RP4lcc
P20RP4lcc Architecture
Mnemonic: P20RP4lcc           Mnemonic: PLCC
Pin Count: 28             Total Product Terms:   64
Extensions: OE D
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
FAIRCHILD                     F20RP4
LATTICE                       RAL20RP4
NATIONAL                      PAL20RP4/20V8
SGS-THOM.                     RAL20RP4
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
%%
%P20RP4A
P20RP4A Architecture
Mnemonic: P20RP4A             Mnemonic: DIP
Pin Count: 24             Total Product Terms:   86
Extensions: OE D IO
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       AMPAL20RP4
_____________________________________________________________
Clock Pin(s): 2               Common OE(s): 16
VCC(s): 28                    GND(s): 14
VEE(s): 1  8  15  22
Input Only: 3  4  5  6  7  9  10  11  12  13
Output Only: 20  21  23  24
Input/Output: 17  18  19  25  26  27
%%
%P20RP4Alcc
P20RP4Alcc Architecture
Mnemonic: P20RP4Alcc          Mnemonic: PLCC
Pin Count: 28             Total Product Terms:   86
Extensions: OE D IO
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       AMPAL20RP4
_____________________________________________________________
Clock Pin(s): 2               Common OE(s): 16
VCC(s): 28                    GND(s): 14
VEE(s): 1  8  15  22
Input Only: 3  4  5  6  7  9  10  11  12  13
Output Only: 20  21  23  24
Input/Output: 17  18  19  25  26  27
%%
%P20RP6
P20RP6 Architecture
Mnemonic: P20RP6              Mnemonic: DIP
Pin Count: 24             Total Product Terms:   64
Extensions: OE D
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
FAIRCHILD                     F20RP6
LATTICE                       RAL20RP6
NATIONAL                      PAL20RP6/20V8
SGS-THOM.                     RAL20RP6
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
%%
%P20RP6lcc
P20RP6lcc Architecture
Mnemonic: P20RP6lcc           Mnemonic: PLCC
Pin Count: 28             Total Product Terms:   64
Extensions: OE D
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
FAIRCHILD                     F20RP6
LATTICE                       RAL20RP6
NATIONAL                      PAL20RP6/20V8
SGS-THOM.                     RAL20RP6
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
%%
%P20RP6A
P20RP6A Architecture
Mnemonic: P20RP6A             Mnemonic: DIP
Pin Count: 24             Total Product Terms:   84
Extensions: OE D IO
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       AMPAL20RP6
_____________________________________________________________
Clock Pin(s): 1  2            Common OE(s): 13  16
VCC(s): 24  28                GND(s): 12  14
VEE(s): 1  8  15  22
Input Only: 2  3  4  5  6  7  8  9  10
            10  11  12  13
Output Only: 16  17  18  19  20  21  23  24  25
Input/Output: 14  15  17  18  22  23  26  27
%%
%P20RP6Alcc
P20RP6Alcc Architecture
Mnemonic: P20RP6Alcc          Mnemonic: PLCC
Pin Count: 28             Total Product Terms:   84
Extensions: OE D IO
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       AMPAL20RP6
_____________________________________________________________
Clock Pin(s): 1  2            Common OE(s): 13  16
VCC(s): 24  28                GND(s): 12  14
VEE(s): 1  8  15  22
Input Only: 2  3  4  5  6  7  8  9  10
            10  11  12  13
Output Only: 16  17  18  19  20  21  23  24  25
Input/Output: 14  15  17  18  22  23  26  27
%%
%P20RP8
P20RP8 Architecture
Mnemonic: P20RP8              Mnemonic: DIP
Pin Count: 24             Total Product Terms:   64
Extensions: D
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
FAIRCHILD                     F20RP8
LATTICE                       RAL20RP8
NATIONAL                      PAL20RP8/20V8
SGS-THOM.                     RAL20RP8
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
%%
%P20RP8lcc
P20RP8lcc Architecture
Mnemonic: P20RP8lcc           Mnemonic: PLCC
Pin Count: 28             Total Product Terms:   64
Extensions: D
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
FAIRCHILD                     F20RP8
LATTICE                       RAL20RP8
NATIONAL                      PAL20RP8/20V8
SGS-THOM.                     RAL20RP8
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
%%
%P20RP8A
P20RP8A Architecture
Mnemonic: P20RP8A             Mnemonic: DIP
Pin Count: 24             Total Product Terms:   82
Extensions: OE D
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       AMPAL20RP8
_____________________________________________________________
Clock Pin(s): 1  2            Common OE(s): 13  16
VCC(s): 24  28                GND(s): 12  14
VEE(s): 1  8  15  22
Input Only: 2  3  4  5  6  7  8  9  10
            10  11  12  13
Output Only: 15  16  17  18  19  20  21  22
              23  24  25  26
Input/Output: 14  17  23  27
%%
%P20RP8Alcc
P20RP8Alcc Architecture
Mnemonic: P20RP8Alcc          Mnemonic: PLCC
Pin Count: 28             Total Product Terms:   82
Extensions: OE D
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       AMPAL20RP8
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
VEE(s):
Input Only:
Output Only:
Input/Output:
%%
%P20RS10
P20RS10 Architecture
Mnemonic: P20RS10             Mnemonic: DIP
Pin Count: 24             Total Product Terms:   80
Extensions: D
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       PAL20RS10
_____________________________________________________________
Clock Pin(s): 1               Common OE(s): 13
VCC(s): 24                    GND(s): 12
Input Only: 2  3  4  5  6  7  8  9  10  11
Output Only: 14  15  16  17  18  19  20  21  22  23
Input/Output:
%%
%P20RS10lcc
P20RS10lcc Architecture
Mnemonic: P20RS10lcc          Mnemonic: PLCC
Pin Count: 28             Total Product Terms:   80
Extensions: D
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       PAL20RS10
_____________________________________________________________
Clock Pin(s): 1               Common OE(s): 13
VCC(s): 24                    GND(s): 12
Input Only: 2  3  4  5  6  7  8  9  10  11
Output Only: 14  15  16  17  18  19  20  21  22  23
Input/Output:
%%
%P20RS4
P20RS4 Architecture
Mnemonic: P20RS4              Mnemonic: DIP
Pin Count: 24             Total Product Terms:   80
Extensions: D OE
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       PAL20RS4
_____________________________________________________________
Clock Pin(s): 1               Common OE(s): 13
VCC(s): 24                    GND(s): 12
Input Only: 2  3  4  5  6  7  8  9  10  11
Output Only: 17  18  19  20
Input/Output: 14  15  16  21  22  23
%%
%P20RS4lcc
P20RS4lcc Architecture
Mnemonic: P20RS4lcc           Mnemonic: PLCC
Pin Count: 28             Total Product Terms:   80
Extensions: D OE
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       PAL20RS4
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
%%
%P20RS8
P20RS8 Architecture
Mnemonic: P20RS8              Mnemonic: DIP
Pin Count: 24             Total Product Terms:   80
Extensions: D OE
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       PAL20RS8
_____________________________________________________________
Clock Pin(s): 1               Common OE(s): 13
VCC(s): 24                    GND(s): 12
Input Only: 2  3  4  5  6  7  8  9  10  11
Output Only: 15  16  17  18  19  20  21  22  23
Input/Output: 14
%%
%P20RS8lcc
P20RS8lcc Architecture
Mnemonic: P20RS8lcc           Mnemonic: PLCC
Pin Count: 28             Total Product Terms:   80
Extensions: D OE
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       PAL20RS8
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
%%
%P20RSP4
P20RSP4 Architecture
Mnemonic: P20RSP4             Mnemonic: DIP
Pin Count: 24             Total Product Terms:   64
Extensions: D OE
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
TI                            TIBPAL20RSP4
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
%%
%P20RSP4lcc
P20RSP4lcc Architecture
Mnemonic: P20RSP4lcc          Mnemonic: PLCC
Pin Count: 28             Total Product Terms:   64
Extensions: D OE
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
TI                            TIBPAL20RSP4
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
%%
%P20RSP6
P20RSP6 Architecture
Mnemonic: P20RSP6             Mnemonic: DIP
Pin Count: 24             Total Product Terms:   64
Extensions: D OE
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
TI                            TIBPAL20RSP6
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
%%
%P20RSP6lcc
P20RSP6lcc Architecture
Mnemonic: P20RSP6lcc          Mnemonic: PLCC
Pin Count: 28             Total Product Terms:   64
Extensions: D OE
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
TI                            TIBPAL20RSP6
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
%%
%P20RSP8
P20RSP8 Architecture
Mnemonic: P20RSP8             Mnemonic: DIP
Pin Count: 24             Total Product Terms:   64
Extensions: D OE
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
TI                            TIBPAL20RSP8
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
%%
%P20RSP8lcc
P20RSP8lcc Architecture
Mnemonic: P20RSP8lcc          Mnemonic: PLCC
Pin Count: 28             Total Product Terms:   64
Extensions: D OE
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
TI                            TIBPAL20RSP8
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
%%
%P20RX8
P20RX8 Architecture
Mnemonic: P20RX8              Mnemonic: DIP
Pin Count: 24             Total Product Terms:   82
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
%%
%P20S10
P20S10 Architecture
Mnemonic: P20S10              Mnemonic: DIP
Pin Count: 24             Total Product Terms:   80
Extensions: OE
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       PAL20S10
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s): 24                    GND(s): 12
Input Only: 1  2  3  4  5  6  7  8  9  10  11  13
Output Only: 14  23
Input/Output: 15  16  17  18  19  20  21  22
%%
%P20S10lcc
P20S10lcc Architecture
Mnemonic: P20S10lcc           Mnemonic: PLCC
Pin Count: 28             Total Product Terms:   80
Extensions: OE
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       PAL20S10
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s): 24                    GND(s): 12
Input Only: 1  2  3  4  5  6  7  8  9  10  11  13
Output Only: 14  23
Input/Output: 15  16  17  18  19  20  21  22
%%
%P20SP8
P20SP8 Architecture
Mnemonic: P20SP8              Mnemonic: DIP
Pin Count: 24             Total Product Terms:   64
Extensions: OE
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
TI                            TIBPAL20SP8
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
%%
%P20SP8lcc
P20SP8lcc Architecture
Mnemonic: P20SP8lcc           Mnemonic: PLCC
Pin Count: 28             Total Product Terms:   64
Extensions: OE
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
TI                            TIBPAL20SP8
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
%%
%P20X10
P20X10 Architecture
Mnemonic: P20X10              Mnemonic: DIP
Pin Count: 24             Total Product Terms:   40
Extensions: D
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       PAL20X10
AMD/MMI                       PAL20X10A
NATIONAL                      PAL20X10/A
TI                            TIBPAL20X10
_____________________________________________________________
Clock Pin(s): 1               Common OE(s): 13
VCC(s): 24                    GND(s): 12
Input Only: 2  3  4  5  6  7  8  9  10  11
Output Only: 14  15  16  17  18  19  20  21  22  23
Input/Output:
_____________________________________________________________
Device Notes:
1.   When writing logic equations for devices containing an
     XOR gate, the $ operator may not be included inside any
     parentheses that change the evaluation order of the
     expression.
2.   When applying DeMorgan's Theorem to an equation
     involving the XOR gate, the expression written first is
     the one negated.
%%
%P20X10lcc
P20X10lcc Architecture
Mnemonic: P20X10lcc           Mnemonic: PLCC
Pin Count: 28             Total Product Terms:   40
Extensions: D
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       PAL20X10
AMD/MMI                       PAL20X10A
NATIONAL                      PAL20X10/A
TI                            TIBPAL20X10
_____________________________________________________________
Clock Pin(s): 1               Common OE(s): 13
VCC(s): 24                    GND(s): 12
Input Only: 2  3  4  5  6  7  8  9  10  11
Output Only: 14  15  16  17  18  19  20  21  22  23
Input/Output:
_____________________________________________________________
Device Notes:
1.   When writing logic equations for devices containing an
     XOR gate, the $ operator may not be included inside any
     parentheses that change the evaluation order of the
     expression.
2.   When applying DeMorgan's Theorem to an equation
     involving the XOR gate, the expression written first is
     the one negated.
%%
%P20X4
P20X4 Architecture
Mnemonic: P20X4               Mnemonic: DIP
Pin Count: 24             Total Product Terms:   40
Extensions: OE D
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       PAL20X4
AMD/MMI                       PAL20X4A
NATIONAL                      PAL20X4/A
TI                            TIBPAL20X4
_____________________________________________________________
Clock Pin(s): 1               Common OE(s): 13
VCC(s): 24                    GND(s): 12
Input Only: 2  3  4  5  6  7  8  9  10  11
Output Only: 17  18  19  20
Input/Output: 14  15  16  21  22  23
_____________________________________________________________
Device Notes:
1.   When writing logic equations for devices containing an
     XOR gate, the $ operator may not be included inside any
     parentheses that change the evaluation order of the
     expression.
2.   When applying DeMorgan's Theorem to an equation
     involving the XOR gate, the expression written first is
     the one negated.
%%
%P20X4lcc
P20X4lcc Architecture
Mnemonic: P20X4lcc            Mnemonic: PLCC
Pin Count: 28             Total Product Terms:   40
Extensions: OE D
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       PAL20X4
AMD/MMI                       PAL20X4A
NATIONAL                      PAL20X4/A
TI                            TIBPAL20X4
_____________________________________________________________
Clock Pin(s): 1               Common OE(s): 13
VCC(s): 24                    GND(s): 12
Input Only: 2  3  4  5  6  7  8  9  10  11
Output Only: 17  18  19  20
Input/Output: 14  15  16  21  22  23
_____________________________________________________________
Device Notes:
1.   When writing logic equations for devices containing an
     XOR gate, the $ operator may not be included inside any
     parentheses that change the evaluation order of the
     expression.
2.   When applying DeMorgan's Theorem to an equation
     involving the XOR gate, the expression written first is
     the one negated.
%%
%P20X8
P20X8 Architecture
Mnemonic: P20X8               Mnemonic: DIP
Pin Count: 24             Total Product Terms:   40
Extensions: OE D
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       PAL20X8
AMD/MMI                       PAL20X8A
NATIONAL                      PAL20X8/A
SPRAGUE                       SPL20XC8
TI                            TIBPAL20X8
_____________________________________________________________
Clock Pin(s): 1               Common OE(s): 13
VCC(s): 24                    GND(s): 12
Input Only: 2  3  4  5  6  7  8  9  10  11
Output Only: 15  16  17  18  19  20  21  22
Input/Output: 14  23
_____________________________________________________________
Device Notes:
1.   When writing logic equations for devices containing an
     XOR gate, the $ operator may not be included inside any
     parentheses that change the evaluation order of the
     expression.
2.   When applying DeMorgan's Theorem to an equation
     involving the XOR gate, the expression written first is
     the one negated.
%%
%P20X8lcc
P20X8lcc Architecture
Mnemonic: P20X8lcc            Mnemonic: PLCC
Pin Count: 28             Total Product Terms:   40
Extensions: OE D
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       PAL20X8
AMD/MMI                       PAL20X8A
NATIONAL                      PAL20X8/A
SPRAGUE                       SPL20XC8
TI                            TIBPAL20X8
_____________________________________________________________
Clock Pin(s): 1               Common OE(s): 13
VCC(s): 24                    GND(s): 12
Input Only: 2  3  4  5  6  7  8  9  10  11
Output Only: 15  16  17  18  19  20  21  22
Input/Output: 14  23
_____________________________________________________________
Device Notes:
1.   When writing logic equations for devices containing an
     XOR gate, the $ operator may not be included inside any
     parentheses that change the evaluation order of the
     expression.
2.   When applying DeMorgan's Theorem to an equation
     involving the XOR gate, the expression written first is
     the one negated.
%%
%P20XRP10
P20XRP10 Architecture
Mnemonic: P20XRP10            Mnemonic: DIP
Pin Count: 24             Total Product Terms:   80
Extensions: D
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       AMPAL20XRP10
_____________________________________________________________
%%
%P20XRP10lcc
P20XRP10lcc Architecture
Mnemonic: P20XRP10lcc         Mnemonic: PLCC
Pin Count: 28             Total Product Terms:   80
Extensions: D
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       AMPAL20XRP10
_____________________________________________________________
%%
%P20XRP4
P20XRP4 Architecture
Mnemonic: P20XRP4             Mnemonic: DIP
Pin Count: 24             Total Product Terms:   86
Extensions: D OE
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       AMPAL20XRP4
_____________________________________________________________
Clock Pin(s): 1  2            Common OE(s): 13  16
VCC(s): 24  28                GND(s): 12  14
VEE(s): 1  8  15  22
Input Only: 2  3  4  5  6  7  8  9  10
            10  11  12  13
Output Only: 17  18  19  20  20  21  23  24
Input/Output: 14  15  16  17  18  19  21  22  23  25  26  27

%%
%P20XRP4lcc
P20XRP4lcc Architecture
Mnemonic: P20XRP4lcc          Mnemonic: PLCC
Pin Count: 28             Total Product Terms:   86
Extensions: D OE
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       AMPAL20XRP4
_____________________________________________________________
Clock Pin(s): 1  2            Common OE(s): 13  16
VCC(s): 24  28                GND(s): 12  14
VEE(s): 1  8  15  22
Input Only: 2  3  4  5  6  7  8  9  10
            10  11  12  13
Output Only: 17  18  19  20  20  21  23  24
Input/Output: 14  15  16  17  18  19  21  22  23  25  26  27
%%
%P20XRP6
P20XRP6 Architecture
Mnemonic: P20XRP6             Mnemonic: DIP
Pin Count: 24             Total Product Terms:   84
Extensions: D OE
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       AMPAL20XRP6
_____________________________________________________________
Clock Pin(s): 1  2            Common OE(s): 13  16
VCC(s): 24  28                GND(s): 12  14
VEE(s): 1  8  15  22
Input Only: 2  3  4  5  6  7  8  9  10
            10  11  12  13
Output Only: 16  17  18  19  19  20  20  21  21  23  24  25
Input/Output: 14  15  17  18  22  23  26  27
%%
%P20XRP6lcc
P20XRP6lcc Architecture
Mnemonic: P20XRP6lcc          Mnemonic: PLCC
Pin Count: 28             Total Product Terms:   84
Extensions: D OE
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       AMPAL20XRP6
_____________________________________________________________
Clock Pin(s): 1  2            Common OE(s): 13  16
VCC(s): 24  28                GND(s): 12  14
VEE(s): 1  8  15  22
Input Only: 2  3  4  5  6  7  8  9  10
            10  11  12  13
Output Only: 16  17  18  19  19  20  20  21  21  23  24  25
Input/Output: 14  15  17  18  22  23  26  27
%%
%P20XRP8
P20XRP8 Architecture
Mnemonic: P20XRP8             Mnemonic: DIP
Pin Count: 24             Total Product Terms:   82
Extensions: D OE
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       AMPAL20XRP8
_____________________________________________________________
Clock Pin(s): 1  2            Common OE(s): 13  16
VCC(s): 24  28                GND(s): 12  14
VEE(s): 1  8  15  22
Input Only: 2  3  4  5  6  7  8  9  10  11  12  13
Output Only: 15  16  18  19  20  21  22  24  25  26
Input/Output: 14  17  23  27
%%
%P20XRP8lcc
P20XRP8lcc Architecture
Mnemonic: P20XRP8lcc          Mnemonic: PLCC
Pin Count: 28             Total Product Terms:   82
Extensions: D OE
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       AMPAL20XRP8
_____________________________________________________________
Clock Pin(s): 1  2            Common OE(s): 13  16
VCC(s): 24  28                GND(s): 12  14
VEE(s): 1  8  15  22
Input Only: 2  3  4  5  6  7  8  9  10  11  12  13
Output Only: 15  16  18  19  20  21  22  24  25  26
Input/Output: 14  17  23  27
%%
%P22CV10Z
P22CV10Z Architecture
Mnemonic: P22CV10Z            Mnemonic: DIP
Pin Count: 24             Total Product Terms:  132
Extensions: OE D AR SP IO DFB INT
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
GOULD                         PEEL22CV10Z
ICT                           PEEL22CV10Z
ICT                           PEEL22CV10A+
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
_____________________________________________________________
Device Notes:
1.  The registered, internal and I/O feedback paths can be
    selected by using the .DFB, .INT and .IO extensions
    respectively. If the feedback type is the same as the
    output (registered feedback for registered output), then
    a feedback extension is not required.
%%
%P22CV10lcc
P22CV10lcc Architecture
Mnemonic: P22CV10lcc          Mnemonic: PLCC
Pin Count: 28             Total Product Terms:  132
Extensions: OE D AR SP IO DFB INT
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
_____________________________________________________________
Device Notes:
1.  The registered, internal and I/O feedback paths can be
    selected by using the .DFB, .INT and .IO extensions
    respectively. If the feedback type is the same as the
    output (registered feedback for registered output), then
    a feedback extension is not required.
%%
%P22IP6
P22IP6 Architecture
Mnemonic: P22IP6              Mnemonic: DIP
Pin Count: 24             Total Product Terms:   72
Extensions: D OE R S T1 T2 AP AR IO
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       PAL22IP6-35
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s): 6                     GND(s): 18
Input Only: 1  2  3  4  5  7  8  9  10  11  12  13  14  22
            23  24

Output Only:
Input/Output: 15  16  17  19  20  21
%%
%P22P10A
P22P10A Architecture
Mnemonic: P22P10A             Mnemonic: DIP
Pin Count: 24             Total Product Terms:   90
Extensions: OE
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       AMPAL22P10
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s): 24  28                GND(s): 12  14
VEE(s): 1  8  15  22
Input Only: 1  2  3  4  5  6  7  8  9  10  11  12  13  16
Output Only:
Input/Output: 14  15  16  17  18  19  20  21  22  23  24  25
              26  27
%%
%P22P10Alcc
P22P10Alcc Architecture
Mnemonic: P22P10Alcc          Mnemonic: PLCC
Pin Count: 28             Total Product Terms:   90
Extensions: OE
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       AMPAL22P10
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
VEE(s):
Input Only:
Output Only:
Input/Output:
%%
%P22RX8
P22RX8 Architecture
Mnemonic: P22RX8              Mnemonic: DIP
Pin Count: 24             Total Product Terms:   82
Extensions: OE D AR AP
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       PAL22RX8
AMD/MMI                       PAL22RX8A
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
%%
%P22RX8lcc
P22RX8lcc Architecture
Mnemonic: P22RX8lcc           Mnemonic: PLCC
Pin Count: 28             Total Product Terms:   82
Extensions: OE D AR AP
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       PAL22RX8
AMD/MMI                       PAL22RX8A
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
%%
%P22V10
P22V10 Architecture
Mnemonic: P22V10              Mnemonic: DIP
Pin Count: 24             Total Product Terms:  132
Extensions: OE D AR SP
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       AMPAL22V10
AMD/MMI                       PALC22V10H
AMD/MMI                       PALC22V10Q
AMD/MMI                       PALCE22V10/4
AMD/MMI                       PALCE22V10H/Q
AMD/MMI                       PALCE22V10Z
ATMEL                         AT22V10/L
ATMEL                         AT22V10B
ATMEL                         AT22LV10/L
ATMEL                         ATF22V10B/L
CYPRESS                       PAL22V10C
CYPRESS                       PAL22V10B
CYPRESS                       PALC22V10
CYPRESS                       PALC22V10D
GAZELLE                       GA22V10
GOULD                         PEEL22CV10
ICT                           PEEL22CV10
ICT                           PEEL22CV10A
NATIONAL                      GAL22V10-10/7
PHILIPS                       PL22V10
TI                            TIBPAL22V10 /A
TI                            TICPAL22V10
TI                            TICPAL22V10Z
_____________________________________________________________
Clock Pin(s): 1               Common OE(s):
VCC(s): 24                    GND(s): 12
Input Only: 1  2  3  4  5  6  7  8  9  10  11  13
Output Only:
Input/Output: 14  15  16  17  18  19  20  21  22  23
%%
%P22V10lcc
P22V10lcc Architecture
Mnemonic: P22V10lcc           Mnemonic: PLCC
Pin Count: 28             Total Product Terms:  132
Extensions: OE D AR SP
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       AMPAL22V10
AMD/MMI                       PALC22V10H
AMD/MMI                       PALC22V10Q
AMD/MMI                       PALCE22V10/4
AMD/MMI                       PALCE22V10H/Q
AMD/MMI                       PALCE22V10Z
ATMEL                         AT22V10/L
ATMEL                         AT22V10B
ATMEL                         AT22LV10/L
ATMEL                         ATF22V10B/L
CYPRESS                       PAL22V10C
CYPRESS                       PAL22V10B
CYPRESS                       PALC22V10
CYPRESS                       PALC22V10D
GAZELLE                       GA22V10
GOULD                         PEEL22CV10
ICT                           PEEL22CV10
ICT                           PEEL22CV10A
NATIONAL                      GAL22V10-10/7
PHILIPS                       PL22V10
TI                            TIBPAL22V10 /A
TI                            TICPAL22V10
TI                            TICPAL22V10Z
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
%%
%P22V10S
P22V10S Architecture
Mnemonic: P22V10S             Mnemonic: DIP
Pin Count: 24             Total Product Terms:  132
Extensions: D T L AR SP OE OEMUX CKMUX LEMUX INT
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
MOTOROLA                      MC22V10S
_____________________________________________________________
Clock Pin(s): 1               Common OE(s):
VCC(s): 24                    GND(s): 12
Input Only: 1  2  3  4  5  6  7  8  9  10  11  13
Output Only:
Input/Output: 14  15  16  17  18  19  20  21  22  23
_____________________________________________________________
Device Notes:
1.  The following superset features are supported:
        T registers, Latches, Inverted clock, Latch enable,
        OE set to VCC/GND.

2.  CLOCK USAGE

    A design using the P22V10S mnemonic can specify for each
    output that the clock for the output register is
    definitely pin 1.
        Ex.  Pin 1  = CLK;
             Pin 21 = X;

             X.D = A;
             X.CKMUX = CLK;

    Since the P22V10S has the ability to invert the clock
    signal, you will need to do the following in your design
    to use this feature:
        Ex.  Pin 1  = CLK;
             Pin 21 = X;

             X.D = A;
             X.CKMUX = !CLK;

    The P22V10S also has the ability to configure the
    macrocell to be a latch.  In CUPL syntax a latch is
    defined by using the following syntax:
        Ex.  Pin 1  = CLK;
             Pin 21 = X;

             X.L = A;
             X.LEMUX = CLK;
    The Latch Enable is defined as active-high.


3.  OUTPUT ENABLE (OE) USAGE

    In a standard 22V10 design the user would either specify
    what each output enable should be or not specify
    anything and let CUPL default the OE product term to
    High (always on). Specifying an OE equation is done in
    the following manner:
        Ex.  Pin 2  = OE1;
             Pin 21 = X;

             X.D = A;
             X.OE = OE1;

    The P22V10S has the ability to set the output enable
    directly to VCC or GND. In CUPL syntax this equates to:
        Ex.  Make outputs always active
             Pin 24 = VCC;
             Pin 21 = X;

             X.D = A;
             X.OEMUX = VCC;

             Make outputs always inactive
             Pin 12 = GND;
             Pin 21 = X;

             X.D = A;
             X.OEMUX = GND;


4.  BURIED NODES AND NODE NUMBERING (for I/O4 and I/O5 only)

    Buried combinatorial and registered nodes are defined by
    using the PINNODE keyword instead of PIN. Configuring a
    macrocell to have a buried combinatorial node allows
    that I/O pin to be used as input. However, configuring a
    macrocell to have a buried register node does NOT allow
    that I/O pin to be used as input.

          DIP Package                 LCC Package
        pin        node             pin        node
        ---        ----             ---        ----
         18         25               21         29
         19         26               23         30


5.  INTERNAL FEEDBACK USAGE

    For I/O's 4 and 5 (pins 18 and 19 DIP, pins 21 and
    23 LCC) the macrocell has both internal and standard
    feedback. Here is how to use these feedbacks in your
    design:

    Combinatorial Output

        Pin  2 = coe;                                 Ŀ
        Pin  3 = in;                in ĳ>ĳPIN
        Pin 15 = out15;                             
        Pin 19 = out19;                            
                                           
        out19 = in;            out19.INT (internal) 
        out19.oe = coe;                
        out15 = out19.int      out19 (default)
              # out19;

    The internal feedback (INT) reflects the value that is
    coming from the AND-OR plane. Therefore, the polarity of
    the output pin does not affect the polarity of the INT
    feedback.
%%
%P22V10Slcc
P22V10Slcc Architecture
Mnemonic: P22V10Slcc          Mnemonic: PLCC
Pin Count: 28             Total Product Terms:  132
Extensions: D T L AR SP OE OEMUX CKMUX LEMUX INT
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
MOTOROLA                      MC22V10S
_____________________________________________________________
Clock Pin(s): 1               Common OE(s):
VCC(s): 24                    GND(s): 12
Input Only: 1  2  3  4  5  6  7  8  9  10  11  13
Output Only:
Input/Output: 14  15  16  17  18  19  20  21  22  23
_____________________________________________________________
Device Notes:
1.  The following superset features are supported:
        T registers, Latches, Inverted clock, Latch enable,
        OE set to VCC/GND.

2.  CLOCK USAGE

    A design using the P22V10S mnemonic can specify for each
    output that the clock for the output register is
    definitely pin 1.
        Ex.  Pin 1  = CLK;
             Pin 21 = X;

             X.D = A;
             X.CKMUX = CLK;

    Since the P22V10S has the ability to invert the clock
    signal, you will need to do the following in your design
    to use this feature:
        Ex.  Pin 1  = CLK;
             Pin 21 = X;

             X.D = A;
             X.CKMUX = !CLK;

    The P22V10S also has the ability to configure the
    macrocell to be a latch.  In CUPL syntax a latch is
    defined by using the following syntax:
        Ex.  Pin 1  = CLK;
             Pin 21 = X;

             X.L = A;
             X.LEMUX = CLK;
    The Latch Enable is defined as active-high.


3.  OUTPUT ENABLE (OE) USAGE

    In a standard 22V10 design the user would either specify
    what each output enable should be or not specify
    anything and let CUPL default the OE product term to
    High (always on). Specifying an OE equation is done in
    the following manner:
        Ex.  Pin 2  = OE1;
             Pin 21 = X;

             X.D = A;
             X.OE = OE1;

    The P22V10S has the ability to set the output enable
    directly to VCC or GND. In CUPL syntax this equates to:
        Ex.  Make outputs always active
             Pin 24 = VCC;
             Pin 21 = X;

             X.D = A;
             X.OEMUX = VCC;

             Make outputs always inactive
             Pin 12 = GND;
             Pin 21 = X;

             X.D = A;
             X.OEMUX = GND;


4.  BURIED NODES AND NODE NUMBERING (for I/O4 and I/O5 only)

    Buried combinatorial and registered nodes are defined by
    using the PINNODE keyword instead of PIN. Configuring a
    macrocell to have a buried combinatorial node allows
    that I/O pin to be used as input. However, configuring a
    macrocell to have a buried register node does NOT allow
    that I/O pin to be used as input.

          DIP Package                 LCC Package
        pin        node             pin        node
        ---        ----             ---        ----
         18         25               21         29
         19         26               23         30


5.  INTERNAL FEEDBACK USAGE

    For I/O's 4 and 5 (pins 18 and 19 DIP, pins 21 and
    23 LCC) the macrocell has both internal and standard
    feedback. Here is how to use these feedbacks in your
    design:

    Combinatorial Output

        Pin  2 = coe;                                 Ŀ
        Pin  3 = in;                in ĳ>ĳPIN
        Pin 15 = out15;                             
        Pin 19 = out19;                            
                                           
        out19 = in;            out19.INT (internal) 
        out19.oe = coe;                
        out15 = out19.int      out19 (default)
              # out19;

    The internal feedback (INT) reflects the value that is
    coming from the AND-OR plane. Therefore, the polarity of
    the output pin does not affect the polarity of the INT
    feedback.
%%
%P22V10T
P22V10T Architecture
Mnemonic: P22V10TLCC          Mnemonic: PLCC
Pin Count: 28             Total Product Terms:  132
Extensions: D AR OE SP
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
TI                            TIBPAL22V10-5C
_____________________________________________________________
Clock Pin(s): 1               Common OE(s):
VCC(s): 8  22                 GND(s): 6  10  20  24
Input Only: 1  2  3  12  13  14  15  16  17  26  27  28
Output Only:
Input/Output: 4  5  7  9  11  18  19  21  23  25
%%
%P22VP10
P22VP10 Architecture
Mnemonic: P22VP10             Mnemonic: DIP
Pin Count: 24             Total Product Terms:  132
Extensions: OE D AR SP IO DFB
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
CYPRESS                       PAL22VP10C
GAZELLE                       GA22VP10
TI                            TIBPAL22VP10
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
_____________________________________________________________
Device Notes:
1.  The registered and I/O feedback paths can be selected by
    using the .DFB and .IO extensions respectively. If the
    feedback type is the same as the output (registered
    feedback for registered output), then a feedback
    extension is not required.
%%
%P22VP10lcc
P22VP10lcc Architecture
Mnemonic: P22VP10lcc          Mnemonic: PLCC
Pin Count: 28             Total Product Terms:  132
Extensions: OE D AR SP IO DFB
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
CYPRESS                       PAL22VP10C
GAZELLE                       GA22VP10
TI                            TIBPAL22VP10
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
_____________________________________________________________
Device Notes:
1.  The registered and I/O feedback paths can be selected by
    using the .DFB and .IO extensions respectively. If the
    feedback type is the same as the output (registered
    feedback for registered output), then a feedback
    extension is not required.
%%
%P22XP10
P22XP10 Architecture
Mnemonic: P22XP10             Mnemonic: DIP
Pin Count: 24             Total Product Terms:   90
Extensions: OE
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       AMPAL22XP10
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s): 24  28                GND(s): 12  14
VEE(s): 1  8  15  22
Input Only: 1  2  3  4  5  6  7  8  9  10  11  12  13  16
Output Only:
Input/Output: 14  15  16  17  18  19  20  21  22  23  24  25
              26  27
%%
%P22XP10lcc
P22XP10lcc Architecture
Mnemonic: P22XP10LCC          Mnemonic: PLCC
Pin Count: 28             Total Product Terms:   90
Extensions: OE
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       AMPAL22XP10
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s): 24  28                GND(s): 12  14
VEE(s): 1  8  15  22
Input Only: 1  2  3  4  5  6  7  8  9  10  11  12  13  16
Output Only:
Input/Output: 14  15  16  17  18  19  20  21  22  23  24  25
              26  27
%%
%P23S8
P23S8 Architecture
Mnemonic: P23S8               Mnemonic: DIP
Pin Count: 20             Total Product Terms:  135
Extensions: OE D AR SP OBS IO DFB
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       AMPAL23S8
GAZELLE                       GA23S8
_____________________________________________________________
Clock Pin(s): 1               Common OE(s):
VCC(s): 20                    GND(s):
Input Only: 2  3  4  5  6  7  8  9  10  11
Output Only:
Input/Output: 12  13  14  15  16  17  18  19
_____________________________________________________________
Device Notes:
1.  The registered and I/O feedback paths can be selected by
    using the .DFB and .IO extensions respectively. If the
    feedback type is the same as the output (registered
    feedback for registered output), then a feedback
    extension is not required.
%%
%P23SV8
P23SV8 Architecture
Mnemonic: P23SV8              Mnemonic: DIP
Pin Count: 20             Total Product Terms:  135
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
GAZELLE                       GA23SV8
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
%%
%P24L10
P24L10 Architecture
Mnemonic: P24L10              Mnemonic: DIP
Pin Count: 28             Total Product Terms:   80
Extensions: OE
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       PAL24L10
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s): 7                     GND(s): 21
Input Only: 1  2  3  4  5  6  8  9  10  11  12  13  14  15
            27  28
Output Only: 16  26
Input/Output: 17  18  19  20  22  23  24  25
%%
%P24R10
P24R10 Architecture
Mnemonic: P24R10              Mnemonic: DIP
Pin Count: 28             Total Product Terms:   80
Extensions: D
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       PAL24R10
_____________________________________________________________
Clock Pin(s): 1               Common OE(s): 15
VCC(s): 7                     GND(s): 21
Input Only: 2  3  4  5  6  8  9  10  11  12  13  14  27  28
Output Only: 16  17  18  19  20  22  23  24  25  26
Input/Output:
%%
%P24R4
P24R4 Architecture
Mnemonic: P24R4               Mnemonic: DIP
Pin Count: 28             Total Product Terms: 80
Extensions: D OE
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       PAL24R4
_____________________________________________________________
Clock Pin(s): 1               Common OE(s): 15
VCC(s): 7                     GND(s): 21
Input Only: 2  3  4  5  6  8  9  10  11  12  13  14  27  28
Output Only: 16  17  18  19  20  22  23  24  25  26
Input/Output:
%%
%P24R8
P24R8 Architecture
Mnemonic: P24R8               Mnemonic: DIP
Pin Count: 28             Total Product Terms: 80
Extensions: D OE
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       PAL24R8
_____________________________________________________________
Clock Pin(s): 1               Common OE(s): 15
VCC(s): 7                     GND(s): 21
Input Only: 2  3  4  5  6  8  9  10  11  12  13  14  27  28
Output Only: 16  17  18  19  20  22  23  24  25  26
Input/Output:
%%
%P26V12
P26V12 Architecture
Mnemonic: P26V12              Mnemonic: DIP/PLCC
Pin Count: 28             Total Product Terms:  150
Extensions: CKMUX OE DFB IO D AR SP
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       PALCE26V12H
SEEQ                          26V12H
_____________________________________________________________
Clock Pin(s): 1  4            Common OE(s):
VCC(s): 21                    GND(s): 7
Input Only: 1  2  3  4  5  6  8  9  10  11  12  13  14  28
Output Only:
Input/Output: 15  16  17  18  19  20  22  23  24  25  26  27
%%
%P29M16
P29M16 Architecture
Mnemonic: P29M16              Mnemonic: DIP
Pin Count: 24             Total Product Terms:  188
Extensions: OE D L DQ LQ AR AP OBS PR CKMUX OEMUX DFB LFB IO
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       PALCE29M16
AMD/MMI                       PALCE29M16/4
_____________________________________________________________
Clock Pin(s):                 Common OE(s): 11
VCC(s): 24                    GND(s): 12
Latch Enable: 1  13
Input Only: 2  11  13  14  23
Output Only:
Input/Output: 3  4  5  6  7  8  9  10  15  16  17  18  19
              20  21  22
_____________________________________________________________
Device Notes:
1.  The output feedback paths can be selected as registered
    only, latched only, I/O only, registered and I/O or
    latched and I/O via the .DFB, .LFB and .IO extensions.
    If the feedback type is the same as the output
    (registered feedback or registered feedback for
    registered output), then a feedback extension is not
    required.
2.  The dual feedback outputs can be treated as buried
    register or latched nodes, allowing the pins to be
    treated as inputs. The buried nodes must be defined in
    NODE or PINNODE statements and the input pins defined in
    PIN statements.
3.  The dual feedback outputs can be treated as registered
    or latched inputs,via the .DQ and .LQ extensions.
4.  Individual clock control is set by writing a .CKMUX
    expression. By default, the clock control is set to
    clock/latch enable pin1, positive edge triggered.
5.  Individual output enable control is set by writing
    either a .OEMUX expression for common control, or a .OE
    expression for banked product term control. By default,
    the output enable control is set to common output enable
    pin 11.
%%
%P29M16lcc
P29M16lcc Architecture
Mnemonic: P29M16lcc           Mnemonic: PLCC
Pin Count: 28             Total Product Terms:  188
Extensions: OE D L DQ LQ AR AP OBS PR CKMUX OEMUX DFB LFB IO
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       PALCE29M16
AMD/MMI                       PALCE29M16/4
_____________________________________________________________
Clock Pin(s):                 Common OE(s): 11
VCC(s): 24                    GND(s): 12
Latch Enable: 1  13
Input Only: 2  11  13  14  23
Output Only:
Input/Output: 3  4  5  6  7  8  9  10  15  16  17  18  19
              20  21  22
_____________________________________________________________
Device Notes:
1.  The output feedback paths can be selected as registered
    only, latched only, I/O only, registered and I/O or
    latched and I/O via the .DFB, .LFB and .IO extensions.
    If the feedback type is the same as the output
    (registered feedback or registered feedback for
    registered output), then a feedback extension is not
    required.
2.  The dual feedback outputs can be treated as buried
    register or latched nodes, allowing the pins to be
    treated as inputs. The buried nodes must be defined in
    NODE or PINNODE statements and the input pins defined in
    PIN statements.
3.  The dual feedback outputs can be treated as registered
    or latched inputs,via the .DQ and .LQ extensions.
4.  Individual clock control is set by writing a .CKMUX
    expression. By default, the clock control is set to
    clock/latch enable pin1, positive edge triggered.
5.  Individual output enable control is set by writing
    either a .OEMUX expression for common control, or a .OE
    expression for banked product term control. By default,
    the output enable control is set to common output enable
    pin 11.
%%
%P29MA16
P29MA16 Architecture
Mnemonic: P29MA16             Mnemonic: DIP
Pin Count: 24             Total Product Terms:  188
Extensions: D L DQ LQ CK LE AR AP OE OBS PR CKMUX OEMUX DFB
            LFB IO
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       PALCE29MA16
AMD/MMI                       PALCE29MA16/4
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
_____________________________________________________________
Device Notes:
1.  The output feedback paths can be selected as registered
    only, latched only, I/O only, registered and I/O or
    latched and I/O via the .DFB, .LFB and .IO extensions.
    If the feedback type is the same as the output
    (registered feedback for registered output), then a
    feedback extension is not required.
2.  The dual feedback outputs can be treated as buried
    register or latched nodes, allowing the pins to be
    treated as inputs. The buried nodes must be defined in
    NODE or PINNODE statements and the input pins defined in
    PIN statements.
3.  The dual feedback outputs can be treated as registered
    or latched inputs via the .DQ and .LQ extensions.
4.  Individual clock or latch enable control is set by
    writing either a .CKMUX expression for synchronous
    control or a .CK expression for asynchronous control. By
    default, the clock control is set to clock/latch enable
    pin 1, positive edge triggered.
5.  Individual output enable control is set by writing
    either a .OEMUX expression or common control, or by a
    .OE expression for banked product term control. By
    default, the output enable control is set to common
    output enable pin 11.
%%
%P29MA16lcc
P29MA16lcc Architecture
Mnemonic: P29MA16lcc          Mnemonic: PLCC
Pin Count: 28             Total Product Terms:  188
Extensions: D L DQ LQ CK LE AR AP OE OBS PR CKMUX OEMUX DFB
            LFB IO
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       PALCE29MA16
AMD/MMI                       PALCE29MA16/4
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
_____________________________________________________________
Device Notes:
1.  The output feedback paths can be selected as registered
    only, latched only, I/O only, registered and I/O or
    latched and I/O via the .DFB, .LFB and .IO extensions.
    If the feedback type is the same as the output
    (registered feedback for registered output), then a
    feedback extension is not required.
2.  The dual feedback outputs can be treated as buried
    register or latched nodes, allowing the pins to be
    treated as inputs. The buried nodes must be defined in
    NODE or PINNODE statements and the input pins defined in
    PIN statements.
3.  The dual feedback outputs can be treated as registered
    or latched inputs via the .DQ and .LQ extensions.
4.  Individual clock or latch enable control is set by
    writing either a .CKMUX expression for synchronous
    control or a .CK expression for asynchronous control. By
    default, the clock control is set to clock/latch enable
    pin 1, positive edge triggered.
5.  Individual output enable control is set by writing
    either a .OEMUX expression or common control, or by a
    .OE expression for banked product term control. By
    default, the output enable control is set to common
    output enable pin 11.
%%
%P32R16
P32R16 Architecture
Mnemonic: P32R16              Mnemonic: DIP
Pin Count: 40             Total Product Terms:  128
Extensions: D
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       PAL32R16
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
%%
%P32R16lcc
P32R16lcc Architecture
Mnemonic: P32R16lcc           Mnemonic: PLCC
Pin Count: 44             Total Product Terms:  128
Extensions: D
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       PAL32R16
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
%%
%P32VX10
P32VX10 Architecture
Mnemonic: P32VX10             Mnemonic: DIP
Pin Count: 24             Total Product Terms:  152
Extensions: OE D SR AP BYP DFB IO
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       PAL32VX10
AMD/MMI                       PAL32VX10A
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
_____________________________________________________________
Device Notes:
1.  Combinatorial outputs have active low polarity, whereas
    registered outputs have programmable polarity.
2.  The output feedback paths can be selected as registered
    only, I/O only, or both, via the .DFB and .IO
    extensions. If the feedback type is the same as the
    output (registered feedback for registered output), then
    a feedback extension is not required.
3.  The outputs can be treated as buried register nodes
    allowing the pins to be treated as inputs. The buried
    nodes must be defined in NODE or PINNODE statements and
    the input pins defined in PIN statements.
%%
%P32VX10lcc
P32VX10lcc Architecture
Mnemonic: P32VX10lcc          Mnemonic: PLCC
Pin Count: 28             Total Product Terms:  152
Extensions: OE D SR AP BYP DFB IO
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       PAL32VX10
AMD/MMI                       PAL32VX10A
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
_____________________________________________________________
Device Notes:
1.  Combinatorial outputs have active low polarity, whereas
    registered outputs have programmable polarity.
2.  The output feedback paths can be selected as registered
    only, I/O only, or both, via the .DFB and .IO
    extensions. If the feedback type is the same as the
    output (registered feedback for registered output), then
    a feedback extension is not required.
3.  The outputs can be treated as buried register nodes
    allowing the pins to be treated as inputs. The buried
    nodes must be defined in NODE or PINNODE statements and
    the input pins defined in PIN statements.
%%
%P64R32
P64R32 Architecture
Mnemonic: P64R32              PLCC Mnemonic: PLCC
Pin Count: 84             Total Product Terms:  256
Extensions: D
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       PAL64R32
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
%%
%P64R32pga
P64R32pga Architecture
Mnemonic: P64R32pga           PLCC Mnemonic: PGA
Pin Count: 88             Total Product Terms:  256
Extensions: D
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       PAL64R32
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
%%
%P6L16
P6L16 Architecture
Mnemonic: P6L16               Mnemonic: DIP
Pin Count: 24             Total Product Terms:   16
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       PAL6L16A
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s): 24                    GND(s): 12
Input Only: 4  5  6  7  8  9
Output Only: 1  2  3  10  11  13  14  15  16  17  18  19
             20  21  22  23
Input/Output:
%%
%P7C330
P7C330 Architecture
Mnemonic: P7C330              Mnemonic: DIP
Pin Count: 28             Total Product Terms:  258
Extensions: D DQ IOD OE SR SP CKMUX OEMUX IMUX
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
CYPRESS                       CY7C330
_____________________________________________________________
%%
%P7C331
P7C331 Architecture
Mnemonic: P7C331              Mnemonic: DIP
Pin Count: 28             Total Product Terms:  216
Extensions: D DQ AR AP IMUX OE CK OEMUX IOD IOAR IOAP IOCK
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
CYPRESS                       CY7C331
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
%%
%P7C332
P7C332 Architecture
Mnemonic: P7C332              Mnemonic: DIP
Pin Count: 28             Total Product Terms:  194
Extensions: DQ LQ LEMUX OE CKMUX OEMUX IO IOD IOL
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
CYPRESS                       CY7C332
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
%%
%P8L14
P8L14 Architecture
Mnemonic: P8L14               Mnemonic: DIP
Pin Count: 24             Total Product Terms:   16
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       PAL8L14A
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s): 24                    GND(s):
Input Only: 3  4  5  6  7  8  9  10
Output Only: 1  2  11  12  13  14  15  16  17  18  19  20
             21  22  23
Input/Output:
%%
%PA7024
PA7024 Architecture
Mnemonic: PA7024              Mnemonic: DIP
Pin Count: 24             Total Product Terms:   80
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
GOULD                         PA7024
ICT                           PA7024
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
%%
%PC224
PC224 Architecture
Mnemonic: PC224               Mnemonic: DIP
Pin Count: 24             Total Product Terms:   72
Extensions: OE D
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
INTEL                         85C224
_____________________________________________________________
Clock Pin(s): 1               Common OE(s):
VCC(s): 24                    GND(s): 12
Input Only: 2  3  4  5  6  7  8  9  10  11  12  13  14  23
Output Only:
Input/Output: 15  16  17  18  19  20  21  22
_____________________________________________________________
Device Notes:
1.  Miser bits:    3200-3201
    Turbo bits:    3202-3203
%%
%PC224lcc
PC224lcc Architecture
Mnemonic: PC224               Mnemonic: PLCC
Pin Count: 28             Total Product Terms:   72
Extensions: OE D
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
INTEL                         85C224
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
_____________________________________________________________
Device Notes:
1.  Miser bits:    3200-3201
    Turbo bits:    3202-3203
%%
%PC508
PC508 Architecture
Mnemonic: PC508               Mnemonic: DIP
Pin Count: 28             Total Product Terms:    8
Extensions: L
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
INTEL                         85C508
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s): 28                    GND(s): 14
Latch Enable: 15              VPP(s): 1
Input Only: 2  3  4  5  6  7  8  9  10  11  12  13  16  17
            26  27
Output Only: 18  19  20  21  22  23  24  25
Input/Output:
%%
%PC960
PC960 Architecture
Mnemonic: PC960               Mnemonic: DIP
Pin Count: 28             Total Product Terms:  16
Extensions: L
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
INTEL                         85C960
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s): 28                    GND(s): 14
Input Only: 1  2  3  4  5  6  7  8  9  15  17  18  19  20
            25  26  27
Output Only: 10  12  13  16  21  22  23  24
Input/Output: 11
_____________________________________________________________
Device Notes:
1.  Does not support simulation.
2.  WAIT960.MAC is needed for creating PLD files.
%%
%PLD9000
PLD9000 Architecture
Mnemonic: PLD9000             Mnemonic: DIP
Pin Count: 100            Total Product Terms:  200
Extensions: OE D CKMUX
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
LOGICAL DEVICES               PLD9000
_____________________________________________________________
Clock Pin(s): 1  2  3  4  5  Common OE(s):
VCC(s):                       GND(s):
Input Only: 6 - 50
Output Only:
Input/Output: 51 - 100
_____________________________________________________________
Device Notes:
This is an imaginary device designed to represent a
generalized PLA. It is intended to be used for designs which
are not targeted for any particular device.  The device
contains 100 pins, 45 inputs, 50 outputs, and 5 clocks. Each
output has individual output enable control and can be
configured in one of four modes.: combinatorial/active low,
combinatorial/active high, D-registered/active low, or
D-registered/active high. There are no power and ground
pins. The pin organization is as follows:
1.  Pin organization:
    Pin 1 -  A common clock input for output pins 51 - 100.
    Pin 2 -  A common clock input for output pins 61 - 70.
    Pin 3 -  A common clock input for output pins 71 - 80.
    Pin 4 -  A common clock input for output pins 81 - 90.
    Pin 5 -  A common clock input for output pins 91 - 100.
    Pins 6 - 50 -  Input pins.
    Pins 51 - 100  Input-Output pins.
2.  Banked clock control is set by writing .CKMUX
    expressions. By default the clock control is set to
    clock pin 1.
3.  There are 200 product terms organized in a PLA format,
    so each is available to any output.
%%
%PLSI
PLSI Architecture
Mnemonic: PLSI                  Mnemonic:
Pin Count:                  Total Product Terms:
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
_____________________________________________________________
Clock Pin(s):                Common OE(s):
VCC(s):                      GND(s):
Input Only:
Output Only:
Input/Output:
_____________________________________________________________
Device Notes:
1.  The pLSI fitter itself is not included with CUPL. This
    must be obtained separately from Lattice.
%%
%PLSI1016_60LH44
PLSI1016_60LH44 Architecture
Mnemonic: PLSI1016_60LH44      Mnemonic: PLCC
Pin Count: 44               Total Product Terms:
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
LATTICE                       pLSI1016-60LH
_____________________________________________________________
Clock Pin(s):                Common OE(s):
VCC(s): 12  34               GND(s): 1  23
Input Only: 2  13  14  24  36
Output Only: 11  33  35
Input/Output: 3  4  5  6  7  8  9  10  15  16  17  18  19 20
              21  22  25  26  27  28  29  30  31  32  37  38
              39  40  41  42  43  44
Internal Nodes: 45 - 108
_____________________________________________________________
Device Notes:
1.  The pLSI fitter itself is not included with CUPL. This
    must be obtained separately from Lattice.
%%
%PLSI1016_60LJ44
PLSI1016_60LJ44 Architecture
Mnemonic: PLSI1016_60LJ44       Mnemonic: JLCC
Pin Count: 44               Total Product Terms:
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
LATTICE                       pLSI1016-60LJ
_____________________________________________________________
Clock Pin(s):                Common OE(s):
VCC(s): 12  34               GND(s): 1  23
Input Only: 2  13  14  24  36
Output Only: 11  33  35
Input/Output: 3  4  5  6  7  8  9  10  15  16  17  18  19 20
              21  22  25  26  27  28  29  30  31  32  37  38
              39  40  41  42  43  44
_____________________________________________________________
Device Notes:
1.  The pLSI fitter itself is not included with CUPL. This
    must be obtained separately from Lattice.
%%
%PLSI1016_60LJ44I
PLSI1016_60LJ44I Architecture
Mnemonic: PLSI1016_60LJ44I      Mnemonic: JLCC
Pin Count: 44               Total Product Terms:
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
LATTICE                       pLSI1016-60LJI
_____________________________________________________________
Clock Pin(s):                Common OE(s):
VCC(s): 12  34               GND(s): 1  23
Input Only: 2  13  14  24  36
Output Only: 11  33  35
Input/Output: 3  4  5  6  7  8  9  10  15  16  17  18  19 20
              21  22  25  26  27  28  29  30  31  32  37  38
              39  40  41  42  43  44
_____________________________________________________________
Device Notes:
1.  The pLSI fitter itself is not included with CUPL. This
    must be obtained separately from Lattice.
%%
%PLSI1016_60LJ44
PLSI1016_60LJ44 Architecture
Mnemonic: PLSI1016_60LJ44       Mnemonic: JLCC
Pin Count: 44               Total Product Terms:
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
LATTICE                       pLSI1016-60LJ
_____________________________________________________________
Clock Pin(s):                Common OE(s):
VCC(s): 12  34               GND(s): 1  23
Input Only: 2  13  14  24  36
Output Only: 11  33  35
Input/Output: 3  4  5  6  7  8  9  10  15  16  17  18  19 20
              21  22  25  26  27  28  29  30  31  32  37  38
              39  40  41  42  43  44
_____________________________________________________________
Device Notes:
1.  The pLSI fitter itself is not included with CUPL. This
    must be obtained separately from Lattice.
%%
%PLSI1016_60LT44
PLSI1016_60LT44 Architecture
Mnemonic: PLSI1016_60LT44       Mnemonic: TQFP
Pin Count: 44               Total Product Terms:
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
LATTICE                       pLSI1016-60LT
_____________________________________________________________
Clock Pin(s):                Common OE(s):
VCC(s): 6  28                GND(s): 17  39
Input Only: 8  18  27  30  40
Output Only: 5  27  29
Input/Output: 1  2  3  4  9  10  11  12  13  14  15  16  19
              20  21  22  23  24  25  26  31  32  33  34  35
              36  37  38  39  41  42  43  44
_____________________________________________________________
Device Notes:
1.  The pLSI fitter itself is not included with CUPL. This
    must be obtained separately from Lattice.
%%
%PLSI1016_80LJ44
PLSI1016_80LJ44 Architecture
Mnemonic: PLSI1016_80LJ44       Mnemonic: JLCC
Pin Count: 44               Total Product Terms:
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
LATTICE                       pLSI1016-80LJ
_____________________________________________________________
Clock Pin(s):                Common OE(s):
VCC(s): 12  34               GND(s): 1  23
Input Only: 2  13  14  24  36
Output Only: 11  33  35
Input/Output: 3  4  5  6  7  8  9  10  15  16  17  18  19 20
              21  22  25  26  27  28  29  30  31  32  37  38
              39  40  41  42  43  44
_____________________________________________________________
Device Notes:
1.  The pLSI fitter itself is not included with CUPL. This
    must be obtained separately from Lattice.
%%
%PLSI1016_80LT44
PLSI1016_80LT44 Architecture
Mnemonic: PLSI1016_80LT44       Mnemonic: TQFP
Pin Count: 44               Total Product Terms:
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
LATTICE                       pLSI1016-80LT
_____________________________________________________________
Clock Pin(s):                Common OE(s):
VCC(s): 6  28                GND(s): 17  39
Input Only: 8  18  27  30  40
Output Only: 5  27  29
Input/Output: 1  2  3  4  9  10  11  12  13  14  15  16  19
              20  21  22  23  24  25  26  31  32  33  34  35
              36  37  38  39  41  42  43  44
_____________________________________________________________
Device Notes:
1.  The pLSI fitter itself is not included with CUPL. This
    must be obtained separately from Lattice.
%%
%PLSI1016_90LJ44
PLSI1016_90LJ44 Architecture
Mnemonic: PLSI1016_90LJ44       Mnemonic: JLCC
Pin Count: 44               Total Product Terms:
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
LATTICE                       pLSI1016-90LJ
_____________________________________________________________
Clock Pin(s):                Common OE(s):
VCC(s): 12  34               GND(s): 1  23
Input Only: 2  13  14  24  36
Output Only: 11  33  35
Input/Output: 3  4  5  6  7  8  9  10  15  16  17  18  19 20
              21  22  25  26  27  28  29  30  31  32  37  38
              39  40  41  42  43  44
_____________________________________________________________
Device Notes:
1.  The pLSI fitter itself is not included with CUPL. This
    must be obtained separately from Lattice.
%%
%PLSI1016_90LT44
PLSI1016_90LT44 Architecture
Mnemonic: PLSI1016_90LT44       Mnemonic: TQFP
Pin Count: 44               Total Product Terms:
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
LATTICE                       pLSI1016-90LT
_____________________________________________________________
Clock Pin(s):                Common OE(s):
VCC(s): 6  28                GND(s): 17  39
Input Only: 8  18  27  30  40
Output Only: 5  27  29
Input/Output: 1  2  3  4  9  10  11  12  13  14  15  16  19
              20  21  22  23  24  25  26  31  32  33  34  35
              36  37  38  39  41  42  43  44
_____________________________________________________________
Device Notes:
1.  The pLSI fitter itself is not included with CUPL. This
    must be obtained separately from Lattice.
%%
%PLSI1016_110LJ44
PLSI1016_110LJ44 Architecture
Mnemonic: PLSI1016_110LJ44      Mnemonic: JLCC
Pin Count: 44               Total Product Terms:
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
LATTICE                       pLSI1016-90LJ
_____________________________________________________________
Clock Pin(s):                Common OE(s):
VCC(s): 12  34               GND(s): 1  23
Input Only: 2  13  14  24  36
Output Only: 11  33  35
Input/Output: 3  4  5  6  7  8  9  10  15  16  17  18  19 20
              21  22  25  26  27  28  29  30  31  32  37  38
              39  40  41  42  43  44
_____________________________________________________________
Device Notes:
1.  The pLSI fitter itself is not included with CUPL. This
    must be obtained separately from Lattice.
%%
%PLSI1024_60LH68
PLSI1024_60LH68 Architecture
Mnemonic: PLSI1024_60LH68       Mnemonic: PLCC
Pin Count: 68               Total Product Terms:
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
LATTICE                       pLSI1024-60LH
_____________________________________________________________
Clock Pin(s):                Common OE(s):
VCC(s): 17  36  53  68       GND(s): 1  18  35  52
Input Only: 2  15  19  20  21  34  49  55
Output Only: 16  50  51  54
Input/Output: 3  4  5  6  7  8  9  10  11  12  13  14  22  23
              24  25  26  27  28  29  30  31  32  33  37  38
              39  40  41  42  43  44  45  46  47  48  56  57
              58  59  60  61  62  63  64  65  66  67
_____________________________________________________________
Device Notes:
1.  The pLSI fitter itself is not included with CUPL. This
    must be obtained separately from Lattice.
%%
%PLSI1024_60LJ68
PLSI1024_60LJ68 Architecture
Mnemonic: PLSI1024_60LJ68       Mnemonic: JLCC
Pin Count: 68               Total Product Terms:
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
LATTICE                       pLSI1024-60LJ
_____________________________________________________________
Clock Pin(s):                Common OE(s):
VCC(s): 17  36  53  68       GND(s): 1  18  35  52
Input Only: 2  15  19  20  21  34  49  55
Output Only: 16  50  51  54
Input/Output: 3  4  5  6  7  8  9  10  11  12  13  14  22  23
              24  25  26  27  28  29  30  31  32  33  37  38
              39  40  41  42  43  44  45  46  47  48  56  57
              58  59  60  61  62  63  64  65  66  67
_____________________________________________________________
Device Notes:
1.  The pLSI fitter itself is not included with CUPL. This
    must be obtained separately from Lattice.
%%
%PLSI1024_60LJ68I
PLSI1024_60LJ68I Architecture
Mnemonic: PLSI1024_60LJ68I      Mnemonic: JLCC
Pin Count: 68               Total Product Terms:
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
LATTICE                       pLSI1024-60LJI
_____________________________________________________________
Clock Pin(s):                Common OE(s):
VCC(s): 17  36  53  68       GND(s): 1  18  35  52
Input Only: 2  15  19  20  21  34  49  55
Output Only: 16  50  51  54
Input/Output: 3  4  5  6  7  8  9  10  11  12  13  14  22  23
              24  25  26  27  28  29  30  31  32  33  37  38
              39  40  41  42  43  44  45  46  47  48  56  57
              58  59  60  61  62  63  64  65  66  67
_____________________________________________________________
Device Notes:
1.  The pLSI fitter itself is not included with CUPL. This
    must be obtained separately from Lattice.
%%
%PLSI1024_80LJ68
PLSI1024_80LJ68 Architecture
Mnemonic: PLSI1024_80LJ68       Mnemonic: JLCC
Pin Count: 68               Total Product Terms:
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
LATTICE                       pLSI1024-80LJ
_____________________________________________________________
Clock Pin(s):                Common OE(s):
VCC(s): 17  36  53  68       GND(s): 1  18  35  52
Input Only: 2  15  19  20  21  34  49  55
Output Only: 16  50  51  54
Input/Output: 3  4  5  6  7  8  9  10  11  12  13  14  22  23
              24  25  26  27  28  29  30  31  32  33  37  38
              39  40  41  42  43  44  45  46  47  48  56  57
              58  59  60  61  62  63  64  65  66  67
_____________________________________________________________
Device Notes:
1.  The pLSI fitter itself is not included with CUPL. This
    must be obtained separately from Lattice.
%%
%PLSI1024_90LJ68
PLSI1024_90LJ68 Architecture
Mnemonic: PLSI1024_90LJ68       Mnemonic: JLCC
Pin Count: 68               Total Product Terms:
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
LATTICE                       pLSI1024-90LJ
_____________________________________________________________
Clock Pin(s):                Common OE(s):
VCC(s): 17  36  53  68       GND(s): 1  18  35  52
Input Only: 2  15  19  20  21  34  49  55
Output Only: 16  50  51  54
Input/Output: 3  4  5  6  7  8  9  10  11  12  13  14  22  23
              24  25  26  27  28  29  30  31  32  33  37  38
              39  40  41  42  43  44  45  46  47  48  56  57
              58  59  60  61  62  63  64  65  66  67
_____________________________________________________________
Device Notes:
1.  The pLSI fitter itself is not included with CUPL. This
    must be obtained separately from Lattice.
%%
%PLSI1032_60LG84
PLSI1032_60LG84 Architecture
Mnemonic: PLSI1032_60LGJ84       Mnemonic: CPGA
Pin Count: 84               Total Product Terms:
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
LATTICE                       pLSI1032-60LG
_____________________________________________________________
Clock Pin(s):                Common OE(s):
VCC(s):                      GND(s):
Input Only:
Output Only:
Input/Output:
_____________________________________________________________
Device Notes:
1.  The pLSI fitter itself is not included with CUPL. This
    must be obtained separately from Lattice.
%%
%PLSI1032_60LJ84
PLSI1032_60LJ84 Architecture
Mnemonic: PLSI1032_60LJ84       Mnemonic: PLCC
Pin Count: 84               Total Product Terms:
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
LATTICE                       pLSI1032-60LJ
_____________________________________________________________
Clock Pin(s):                Common OE(s):
VCC(s): 21  65               GND(s): 1  22  43  64
Input Only: 2  19  23  24  25  42  44  61  67  84
Output Only: 20  62  63  66
Input/Output: 3  4  5  6  7  8  9  10  11  12  13  14  15  16
              17  18  26  27  28  29  30  31  32  33  34  35
              36  37  38  39  40  41  45  46  47  48  49  50
              51  52  53  54  55  56  57  58  59  60  68  69
              70  71  72  73  74  75  76  77  78  79  80  81
              82  83
_____________________________________________________________
Device Notes:
1.  The pLSI fitter itself is not included with CUPL. This
    must be obtained separately from Lattice.
%%
%PLSI1032_60LJ84I
PLSI1032_60LJ84I Architecture
Mnemonic: PLSI1032_60LJ84I      Mnemonic: PLCC
Pin Count: 84               Total Product Terms:
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
LATTICE                       pLSI1032-60LJI
_____________________________________________________________
Clock Pin(s):                Common OE(s):
VCC(s): 21  65               GND(s): 1  22  43  64
Input Only: 2  19  23  24  25  42  44  61  67  84
Output Only: 20  62  63  66
Input/Output: 3  4  5  6  7  8  9  10  11  12  13  14  15  16
              17  18  26  27  28  29  30  31  32  33  34  35
              36  37  38  39  40  41  45  46  47  48  49  50
              51  52  53  54  55  56  57  58  59  60  68  69
              70  71  72  73  74  75  76  77  78  79  80  81
              82  83
_____________________________________________________________
Device Notes:
1.  The pLSI fitter itself is not included with CUPL. This
    must be obtained separately from Lattice.
%%
%PLSI1032_60LT100
PLSI1032_60LT100 Architecture
Mnemonic: PLSI1032_60LT100      Mnemonic: TQFP
Pin Count: 100              Total Product Terms:
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
LATTICE                       pLSI1032-60LT
_____________________________________________________________
Clock Pin(s):                Common OE(s):
VCC(s):                      GND(s):
Input Only:
Output Only:
Input/Output:

_____________________________________________________________
Device Notes:
1.  The pLSI fitter itself is not included with CUPL. This
    must be obtained separately from Lattice.
%%
%PLSI1032_80LJ84
PLSI1032_80LJ84 Architecture
Mnemonic: PLSI1032_80LJ84       Mnemonic: PLCC
Pin Count: 84               Total Product Terms:
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
LATTICE                       pLSI1032-80LJ
_____________________________________________________________
Clock Pin(s):                Common OE(s):
VCC(s): 21  65               GND(s): 1  22  43  64
Input Only: 2  19  23  24  25  42  44  61  67  84
Output Only: 20  62  63  66
Input/Output: 3  4  5  6  7  8  9  10  11  12  13  14  15  16
              17  18  26  27  28  29  30  31  32  33  34  35
              36  37  38  39  40  41  45  46  47  48  49  50
              51  52  53  54  55  56  57  58  59  60  68  69
              70  71  72  73  74  75  76  77  78  79  80  81
              82  83
_____________________________________________________________
Device Notes:
1.  The pLSI fitter itself is not included with CUPL. This
    must be obtained separately from Lattice.
%%
%PLSI1032_80LT100
PLSI1032_80LT100 Architecture
Mnemonic: PLSI1032_80LT100      Mnemonic: TQFP
Pin Count: 100              Total Product Terms:
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
LATTICE                       pLSI1032-80LT
_____________________________________________________________
Clock Pin(s):                Common OE(s):
VCC(s):                      GND(s):
Input Only:
Output Only:
Input/Output:

_____________________________________________________________
Device Notes:
1.  The pLSI fitter itself is not included with CUPL. This
    must be obtained separately from Lattice.
%%
%PLSI1032_90LJ84
PLSI1032_90LJ84 Architecture
Mnemonic: PLSI1032_90LJ84       Mnemonic: PLCC
Pin Count: 84               Total Product Terms:
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
LATTICE                       pLSI1032-90LJ
_____________________________________________________________
Clock Pin(s):                Common OE(s):
VCC(s): 21  65               GND(s): 1  22  43  64
Input Only: 2  19  23  24  25  42  44  61  67  84
Output Only: 20  62  63  66
Input/Output: 3  4  5  6  7  8  9  10  11  12  13  14  15  16
              17  18  26  27  28  29  30  31  32  33  34  35
              36  37  38  39  40  41  45  46  47  48  49  50
              51  52  53  54  55  56  57  58  59  60  68  69
              70  71  72  73  74  75  76  77  78  79  80  81
              82  83
_____________________________________________________________
Device Notes:
1.  The pLSI fitter itself is not included with CUPL. This
    must be obtained separately from Lattice.
%%
%PLSI1032_90LT100
PLSI1032_90LT100 Architecture
Mnemonic: PLSI1032_90LT100      Mnemonic: TQFP
Pin Count: 100              Total Product Terms:
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
LATTICE                       pLSI1032-90LT
_____________________________________________________________
Clock Pin(s):                Common OE(s):
VCC(s):                      GND(s):
Input Only:
Output Only:
Input/Output:

_____________________________________________________________
Device Notes:
1.  The pLSI fitter itself is not included with CUPL. This
    must be obtained separately from Lattice.
%%
%PLSI1048_50LQ120
PLSI1048_50LQ120 Architecture
Mnemonic: PLSI1048_50LQ120      Mnemonic: PQFP
Pin Count: 120              Total Product Terms:
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
LATTICE                       pLSI1048-50LQ
_____________________________________________________________
Clock Pin(s):                Common OE(s):
VCC(s): 15  45  77  107         GND(s): 16  46  76  106
Input Only: 13  17  18  19  44  47  48  73  79  104  105  108
Output Only: 14  74  75  78
Input/Output: 1  2  3  4  5  6  7  8  9  10  11  12   20  21
              22  23  24  25  26  27  28  29  30  31  32  33
              34  35  36  37  38  39  40  41  42  43  49  50
              51  52  53  54  55  56  57  58  59  60  61  62
              63  64  65  66  67  68  69  70  71  72  80  81
              82  83  84  85  86  87  88  89  90  91  92  93
              94  95  96  97  98  99  100  101 102  103  109
              110  111  112  113  114  115  116  117  118
              119  120
_____________________________________________________________
Device Notes:
1.  The pLSI fitter itself is not included with CUPL. This
    must be obtained separately from Lattice.
%%
%PLSI1048_50LQ120I
PLSI1048_50LQ120I Architecture
Mnemonic: PLSI1048_50LQ120I     Mnemonic: PQFP
Pin Count: 120              Total Product Terms:
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
LATTICE                       pLSI1048-50LQI
_____________________________________________________________
Clock Pin(s):                Common OE(s):
VCC(s): 15  45  77  107         GND(s): 16  46  76  106
Input Only: 13  17  18  19  44  47  48  73  79  104  105  108
Output Only: 14  74  75  78
Input/Output: 1  2  3  4  5  6  7  8  9  10  11  12   20  21
              22  23  24  25  26  27  28  29  30  31  32  33
              34  35  36  37  38  39  40  41  42  43  49  50
              51  52  53  54  55  56  57  58  59  60  61  62
              63  64  65  66  67  68  69  70  71  72  80  81
              82  83  84  85  86  87  88  89  90  91  92  93
              94  95  96  97  98  99  100  101 102  103  109
              110  111  112  113  114  115  116  117  118
              119  120
_____________________________________________________________
Device Notes:
1.  The pLSI fitter itself is not included with CUPL. This
    must be obtained separately from Lattice.
%%
%PLSI1048_70LQ120
PLSI1048_70LQ120 Architecture
Mnemonic: PLSI1048_70LQ120      Mnemonic: PQFP
Pin Count: 120              Total Product Terms:
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
LATTICE                       pLSI1048-70LQ
_____________________________________________________________
Clock Pin(s):                Common OE(s):
VCC(s): 15  45  77  107         GND(s): 16  46  76  106
Input Only: 13  17  18  19  44  47  48  73  79  104  105  108
Output Only: 14  74  75  78
Input/Output: 1  2  3  4  5  6  7  8  9  10  11  12   20  21
              22  23  24  25  26  27  28  29  30  31  32  33
              34  35  36  37  38  39  40  41  42  43  49  50
              51  52  53  54  55  56  57  58  59  60  61  62
              63  64  65  66  67  68  69  70  71  72  80  81
              82  83  84  85  86  87  88  89  90  91  92  93
              94  95  96  97  98  99  100  101 102  103  109
              110  111  112  113  114  115  116  117  118
              119  120
_____________________________________________________________
Device Notes:
1.  The pLSI fitter itself is not included with CUPL. This
    must be obtained separately from Lattice.
%%
%PLSI1048_80LQ120
PLSI1048_80LQ120 Architecture
Mnemonic: PLSI1048_80LQ120      Mnemonic: PQFP
Pin Count: 120              Total Product Terms:
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
LATTICE                       pLSI1048-80LQ
_____________________________________________________________
Clock Pin(s):                Common OE(s):
VCC(s): 15  45  77  107         GND(s): 16  46  76  106
Input Only: 13  17  18  19  44  47  48  73  79  104  105  108
Output Only: 14  74  75  78
Input/Output: 1  2  3  4  5  6  7  8  9  10  11  12   20  21
              22  23  24  25  26  27  28  29  30  31  32  33
              34  35  36  37  38  39  40  41  42  43  49  50
              51  52  53  54  55  56  57  58  59  60  61  62
              63  64  65  66  67  68  69  70  71  72  80  81
              82  83  84  85  86  87  88  89  90  91  92  93
              94  95  96  97  98  99  100  101 102  103  109
              110  111  112  113  114  115  116  117  118
              119  120
_____________________________________________________________
Device Notes:
1.  The pLSI fitter itself is not included with CUPL. This
    must be obtained separately from Lattice.
%%
%PLSI1048C_50LG33
PLSI1048C_50LG33 Architecture
Mnemonic: PLSI1048C_50LG33      Mnemonic: CPGA
Pin Count: 133              Total Product Terms:
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
LATTICE                       pLSI1048C-50LG
_____________________________________________________________
Clock Pin(s):                Common OE(s):
VCC(s):                         GND(s):
Input Only:
Output Only:
Input/Output:

_____________________________________________________________
Device Notes:
1.  The pLSI fitter itself is not included with CUPL. This
    must be obtained separately from Lattice.
%%
%PLSI1048C_50LQ28
PLSI1048C_50LQ28 Architecture
Mnemonic: PLSI1048C_50LQ28      Mnemonic: PQFP
Pin Count: 128              Total Product Terms:
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
LATTICE                       pLSI1048C-50LQ
_____________________________________________________________
Clock Pin(s):                Common OE(s):
VCC(s):                         GND(s):
Input Only:
Output Only:
Input/Output:
_____________________________________________________________
Device Notes:
1.  The pLSI fitter itself is not included with CUPL. This
    must be obtained separately from Lattice.
%%
%PLSI1048C_50LQ8I
PLSI1048C_50LQ8I Architecture
Mnemonic: PLSI1048C_50LQ8I      Mnemonic: PQFP
Pin Count: 128              Total Product Terms:
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
LATTICE                       pLSI1048C-50LQI
_____________________________________________________________
Clock Pin(s):                Common OE(s):
VCC(s):                         GND(s):
Input Only:
Output Only:
Input/Output:
_____________________________________________________________
Device Notes:
1.  The pLSI fitter itself is not included with CUPL. This
    must be obtained separately from Lattice.
%%
%PLSI1048C_70LQ28
PLSI1048C_70LQ28 Architecture
Mnemonic: PLSI1048C_70LQ28      Mnemonic: PQFP
Pin Count: 128              Total Product Terms:
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
LATTICE                       pLSI1048C-70LQ
_____________________________________________________________
Clock Pin(s):                Common OE(s):
VCC(s):                         GND(s):
Input Only:
Output Only:
Input/Output:
_____________________________________________________________
Device Notes:
1.  The pLSI fitter itself is not included with CUPL. This
    must be obtained separately from Lattice.
%%
%PLSI2032_110LJ44
PLSI2032_110LJ44 Architecture
Mnemonic: PLSI2032_110LJ44      Mnemonic: PLCC
Pin Count: 44               Total Product Terms:
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
LATTICE                       pLSI2032-110LJ
_____________________________________________________________
Clock Pin(s):                Common OE(s):
VCC(s): 12  34               GND(s): 1  23
Input Only: 2  13  14  24  36
Output Only: 11  33  35
Input/Output: 3  4  5  6  7  8  9  10  15  16  17  18  19 20
              21  22  25  26  27  28  29  30  31  32  37  38
              39  40  41  42  43  44
_____________________________________________________________
Device Notes:
1.  The pLSI fitter itself is not included with CUPL. This
    must be obtained separately from Lattice.
%%
%PLSI2032_110LT44
PLSI2032_110LT44 Architecture
Mnemonic: PLSI2032_110LT44      Mnemonic: TQFP
Pin Count: 44               Total Product Terms:
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
LATTICE                       pLSI2032-110LT
_____________________________________________________________
Clock Pin(s):                Common OE(s):
VCC(s): 6  28                GND(s): 17  39
Input Only: 8  18  27  30  40
Output Only: 5  27  29
Input/Output: 1  2  3  4  9  10  11  12  13  14  15  16  19
              20  21  22  23  24  25  26  31  32  33  34  35
              36  37  38  39  41  42  43  44
_____________________________________________________________
Device Notes:
1.  The pLSI fitter itself is not included with CUPL. This
    must be obtained separately from Lattice.
%%
%PLSI2032_135LJ44
PLSI2032_135LJ44 Architecture
Mnemonic: PLSI2032_135LJ44      Mnemonic: PLCC
Pin Count: 44               Total Product Terms:
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
LATTICE                       pLSI2032-135LJ
_____________________________________________________________
Clock Pin(s):                Common OE(s):
VCC(s): 12  34               GND(s): 1  23
Input Only: 2  13  14  24  36
Output Only: 11  33  35
Input/Output: 3  4  5  6  7  8  9  10  15  16  17  18  19 20
              21  22  25  26  27  28  29  30  31  32  37  38
              39  40  41  42  43  44
_____________________________________________________________
Device Notes:
1.  The pLSI fitter itself is not included with CUPL. This
    must be obtained separately from Lattice.
%%
%PLSI2032_135LT44
PLSI2032_135LT44 Architecture
Mnemonic: PLSI2032_135LT44      Mnemonic: TQFP
Pin Count: 44               Total Product Terms:
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
LATTICE                       pLSI2032-135LT
_____________________________________________________________
Clock Pin(s):                Common OE(s):
VCC(s): 6  28                GND(s): 17  39
Input Only: 8  18  27  30  40
Output Only: 5  27  29
Input/Output: 1  2  3  4  9  10  11  12  13  14  15  16  19
              20  21  22  23  24  25  26  31  32  33  34  35
              36  37  38  39  41  42  43  44
_____________________________________________________________
Device Notes:
1.  The pLSI fitter itself is not included with CUPL. This
    must be obtained separately from Lattice.
%%
%PLSI2032_150LJ44
PLSI2032_150LJ44 Architecture
Mnemonic: PLSI2032_150LJ44      Mnemonic: PLCC
Pin Count: 44               Total Product Terms:
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
LATTICE                       pLSI2032-150LJ
_____________________________________________________________
Clock Pin(s):                Common OE(s):
VCC(s): 12  34               GND(s): 1  23
Input Only: 2  13  14  24  36
Output Only: 11  33  35
Input/Output: 3  4  5  6  7  8  9  10  15  16  17  18  19 20
              21  22  25  26  27  28  29  30  31  32  37  38
              39  40  41  42  43  44
_____________________________________________________________
Device Notes:
1.  The pLSI fitter itself is not included with CUPL. This
    must be obtained separately from Lattice.
%%
%PLSI2032_150LT44
PLSI2032_150LT44 Architecture
Mnemonic: PLSI2032_150LT44      Mnemonic: TQFP
Pin Count: 44               Total Product Terms:
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
LATTICE                       pLSI2032-150LT
_____________________________________________________________
Clock Pin(s):                Common OE(s):
VCC(s): 6  28                GND(s): 17  39
Input Only: 8  18  27  30  40
Output Only: 5  27  29
Input/Output: 1  2  3  4  9  10  11  12  13  14  15  16  19
              20  21  22  23  24  25  26  31  32  33  34  35
              36  37  38  39  41  42  43  44
_____________________________________________________________
Device Notes:
1.  The pLSI fitter itself is not included with CUPL. This
    must be obtained separately from Lattice.
%%
%PLSI2032_80LJ44
PLSI2032_80LJ44 Architecture
Mnemonic: PLSI2032_80LJ44      Mnemonic: PLCC
Pin Count: 44               Total Product Terms:
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
LATTICE                       pLSI2032-80LJ
_____________________________________________________________
Clock Pin(s):                Common OE(s):
VCC(s): 12  34               GND(s): 1  23
Input Only: 2  13  14  24  36
Output Only: 11  33  35
Input/Output: 3  4  5  6  7  8  9  10  15  16  17  18  19 20
              21  22  25  26  27  28  29  30  31  32  37  38
              39  40  41  42  43  44
_____________________________________________________________
Device Notes:
1.  The pLSI fitter itself is not included with CUPL. This
    must be obtained separately from Lattice.
%%
%PLSI2032_80LT44
PLSI2032_80LT44 Architecture
Mnemonic: PLSI2032_80LT44      Mnemonic: TQFP
Pin Count: 44               Total Product Terms:
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
LATTICE                       pLSI2032-80LT
_____________________________________________________________
Clock Pin(s):                Common OE(s):
VCC(s): 6  28                GND(s): 17  39
Input Only: 8  18  27  30  40
Output Only: 5  27  29
Input/Output: 1  2  3  4  9  10  11  12  13  14  15  16  19
              20  21  22  23  24  25  26  31  32  33  34  35
              36  37  38  39  41  42  43  44
_____________________________________________________________
Device Notes:
1.  The pLSI fitter itself is not included with CUPL. This
    must be obtained separately from Lattice.
%%
%PLSI2064_100LJ84
PLSI2064_100LJ84 Architecture
Mnemonic: PLSI2064_100LJ84      Mnemonic: PLCC
Pin Count: 84               Total Product Terms:
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
LATTICE                       pLSI2064-100LJ
_____________________________________________________________
Clock Pin(s):                Common OE(s):
VCC(s): 21  65               GND(s): 1  22  43  64
Input Only: 2  19  23  24  25  42  44  61  67  84
Output Only: 20  62  63  66
Input/Output: 3  4  5  6  7  8  9  10  11  12  13  14  15  16
              17  18  26  27  28  29  30  31  32  33  34  35
              36  37  38  39  40  41  45  46  47  48  49  50
              51  52  53  54  55  56  57  58  59  60  68  69
              70  71  72  73  74  75  76  77  78  79  80  81
              82  83
_____________________________________________________________
Device Notes:
1.  The pLSI fitter itself is not included with CUPL. This
    must be obtained separately from Lattice.
%%
%PLSI2064_10LT100
PLSI2064_10LT100 Architecture
Mnemonic: PLSI2064_10LT100      Mnemonic: TQFP
Pin Count: 100              Total Product Terms:
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
LATTICE                       pLSI2064-100LT
_____________________________________________________________
Clock Pin(s):                Common OE(s):
VCC(s):                      GND(s):
Input Only:
Output Only:
Input/Output:

_____________________________________________________________
Device Notes:
1.  The pLSI fitter itself is not included with CUPL. This
    must be obtained separately from Lattice.
%%
%PLSI2064_125LJ84
PLSI2064_125LJ84 Architecture
Mnemonic: PLSI2064_125LJ84      Mnemonic: PLCC
Pin Count: 84               Total Product Terms:
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
LATTICE                       pLSI2064-125LJ
_____________________________________________________________
Clock Pin(s):                Common OE(s):
VCC(s): 21  65               GND(s): 1  22  43  64
Input Only: 2  19  23  24  25  42  44  61  67  84
Output Only: 20  62  63  66
Input/Output: 3  4  5  6  7  8  9  10  11  12  13  14  15  16
              17  18  26  27  28  29  30  31  32  33  34  35
              36  37  38  39  40  41  45  46  47  48  49  50
              51  52  53  54  55  56  57  58  59  60  68  69
              70  71  72  73  74  75  76  77  78  79  80  81
              82  83
_____________________________________________________________
Device Notes:
1.  The pLSI fitter itself is not included with CUPL. This
    must be obtained separately from Lattice.
%%
%PLSI2064_12LT100
PLSI2064_12LT100 Architecture
Mnemonic: PLSI2064_12LT100      Mnemonic: TQFP
Pin Count: 100              Total Product Terms:
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
LATTICE                       pLSI2064-125LT
_____________________________________________________________
Clock Pin(s):                Common OE(s):
VCC(s):                      GND(s):
Input Only:
Output Only:
Input/Output:

_____________________________________________________________
Device Notes:
1.  The pLSI fitter itself is not included with CUPL. This
    must be obtained separately from Lattice.
%%
%PLSI2064_80LJ84
PLSI2064_80LJ84 Architecture
Mnemonic: PLSI2064_80LJ84      Mnemonic: PLCC
Pin Count: 84               Total Product Terms:
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
LATTICE                       pLSI2064-80LJ
_____________________________________________________________
Clock Pin(s):                Common OE(s):
VCC(s): 21  65               GND(s): 1  22  43  64
Input Only: 2  19  23  24  25  42  44  61  67  84
Output Only: 20  62  63  66
Input/Output: 3  4  5  6  7  8  9  10  11  12  13  14  15  16
              17  18  26  27  28  29  30  31  32  33  34  35
              36  37  38  39  40  41  45  46  47  48  49  50
              51  52  53  54  55  56  57  58  59  60  68  69
              70  71  72  73  74  75  76  77  78  79  80  81
              82  83
_____________________________________________________________
Device Notes:
1.  The pLSI fitter itself is not included with CUPL. This
    must be obtained separately from Lattice.
%%
%PLSI2064_80LT100
PLSI2064_80LT100 Architecture
Mnemonic: PLSI2064_80LT100      Mnemonic: TQFP
Pin Count: 100              Total Product Terms:
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
LATTICE                       pLSI2064-80LT
_____________________________________________________________
Clock Pin(s):                Common OE(s):
VCC(s):                      GND(s):
Input Only:
Output Only:
Input/Output:

_____________________________________________________________
Device Notes:
1.  The pLSI fitter itself is not included with CUPL. This
    must be obtained separately from Lattice.
%%
%PLSI2096_10LQ128
PLSI2096_10LQ128 Architecture
Mnemonic: PLSI2096_10LQ128      Mnemonic: PQFP
Pin Count: 128              Total Product Terms:
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
LATTICE                       pLSI2096-100LQ
_____________________________________________________________
Clock Pin(s):                Common OE(s):
VCC(s):                         GND(s):
Input Only:
Output Only:
Input/Output:
_____________________________________________________________
Device Notes:
1.  The pLSI fitter itself is not included with CUPL. This
    must be obtained separately from Lattice.
%%
%PLSI2096_120LQ128
PLSI2096_12LQ128 Architecture
Mnemonic: PLSI2096_12LQ128      Mnemonic: PQFP
Pin Count: 128              Total Product Terms:
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
LATTICE                       pLSI2096-125LQ
_____________________________________________________________
Clock Pin(s):                Common OE(s):
VCC(s):                         GND(s):
Input Only:
Output Only:
Input/Output:
_____________________________________________________________
Device Notes:
1.  The pLSI fitter itself is not included with CUPL. This
    must be obtained separately from Lattice.
%%
%PLSI2096_80LQ128
PLSI2096_80LQ128 Architecture
Mnemonic: PLSI2096_80LQ128      Mnemonic: PQFP
Pin Count: 128              Total Product Terms:
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
LATTICE                       pLSI2096-80LQ
_____________________________________________________________
Clock Pin(s):                Common OE(s):
VCC(s):                         GND(s):
Input Only:
Output Only:
Input/Output:
_____________________________________________________________
Device Notes:
1.  The pLSI fitter itself is not included with CUPL. This
    must be obtained separately from Lattice.
%%
%PLSI2128_10LM160
PLSI2128_10LM160 Architecture
Mnemonic: PLSI2128_10LM160      Mnemonic: MQUAD
Pin Count: 160              Total Product Terms:
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
LATTICE                       pLSI2128-100LM
_____________________________________________________________
Clock Pin(s):                Common OE(s):
VCC(s):                         GND(s):
Input Only:
Output Only:
Input/Output:
_____________________________________________________________
Device Notes:
1.  The pLSI fitter itself is not included with CUPL. This
    must be obtained separately from Lattice.
%%
%PLSI2128_80LM160
PLSI2128_80LM160 Architecture
Mnemonic: PLSI2128_80LM160      Mnemonic: MQUAD
Pin Count: 160              Total Product Terms:
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
LATTICE                       pLSI2128-80LM
_____________________________________________________________
Clock Pin(s):                Common OE(s):
VCC(s):                         GND(s):
Input Only:
Output Only:
Input/Output:
_____________________________________________________________
Device Notes:
1.  The pLSI fitter itself is not included with CUPL. This
    must be obtained separately from Lattice.
%%
%PLSI3256_50LG167
PLSI3256_50LG167 Architecture
Mnemonic: PLSI3256_50LG167      Mnemonic: CPGA
Pin Count: 167              Total Product Terms:
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
LATTICE                       pLSI3256-50LG
_____________________________________________________________
Clock Pin(s):                Common OE(s):
VCC(s):                         GND(s):
Input Only:
Output Only:
Input/Output:
_____________________________________________________________
Device Notes:
1.  The pLSI fitter itself is not included with CUPL. This
    must be obtained separately from Lattice.
%%
%PLSI3256_50LM160
PLSI3256_50LM160 Architecture
Mnemonic: PLSI3256_50LM160      Mnemonic: MQUAD
Pin Count: 167              Total Product Terms:
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
LATTICE                       pLSI3256-50LM
_____________________________________________________________
Clock Pin(s):                Common OE(s):
VCC(s):                         GND(s):
Input Only:
Output Only:
Input/Output:
_____________________________________________________________
Device Notes:
1.  The pLSI fitter itself is not included with CUPL. This
    must be obtained separately from Lattice.
%%
%PLSI3256_70LG167
PLSI3256_70LG167 Architecture
Mnemonic: PLSI3256_70LG167      Mnemonic: CPGA
Pin Count: 167              Total Product Terms:
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
LATTICE                       pLSI3256-70LG
_____________________________________________________________
Clock Pin(s):                Common OE(s):
VCC(s):                         GND(s):
Input Only:
Output Only:
Input/Output:
_____________________________________________________________
Device Notes:
1.  The pLSI fitter itself is not included with CUPL. This
    must be obtained separately from Lattice.
%%
%PLSI3256_70LM160
PLSI3256_70LM160 Architecture
Mnemonic: PLSI3256_70LM160      Mnemonic: MQUAD
Pin Count: 167              Total Product Terms:
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
LATTICE                       pLSI3256-70LM
_____________________________________________________________
Clock Pin(s):                Common OE(s):
VCC(s):                         GND(s):
Input Only:
Output Only:
Input/Output:
_____________________________________________________________
Device Notes:
1.  The pLSI fitter itself is not included with CUPL. This
    must be obtained separately from Lattice.
%%
%PLX448
PLX448 Architecture
Mnemonic: PLX448              Mnemonic: DIP
Pin Count: 24             Total Product Terms:   98
Extensions: OE D AR SP TEC IO
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
PLX TECH.                     PLX448
PLX TECH.                     PLX464
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
_____________________________________________________________
Device Notes:
1.  The output feedback paths can be selected as internal
    only, I/O only, or both, via the .INT and .IO
    extensions. If the feedback type is the same as the
    output (internal feedback for registered output), then a
    feedback extension is not required.
2.  The outputs can be treated as a buried register or
    combinatorial nodes, allowing the pins to be treated as
    inputs.  The buried nodes must be defined in NODE or
    PINNODE statements and the input pins defined in PIN
    statements.
3.  The 48mA output pins can be programmed to behave as open
    collector outputs, by writing .TEC expressions.
%%
%PZ3032_plcc44
PZ3032_plcc44 Architecture
Mnemonic: PZ3032_plcc44         Mnemonic: PLCC
Pin Count: 44               Total Product Terms:
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
PHILIPS                       PZ3032-plcc44
_____________________________________________________________
Clock Pin(s): 4  43          Common OE(s):
VCC(s): 3  15  23  35           GND(s): 10  22  30  42
Input Only: 1  2  43  44
Output Only:
Input/Output: 5  6  7  8  9  11  12  13  14  16  17  18  19
              20  21  24  25  26  27  28  29  31  32  33  34
              36  37  38  39  40  41
_____________________________________________________________
Device Notes:
%%
%PZ3032_qfp44
PZ3032_qfp44 Architecture
Mnemonic: PZ3032_qfp44          Mnemonic: QFP
Pin Count: 44               Total Product Terms:
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
PHILIPS                       PZ3032-qfp44
_____________________________________________________________
Clock Pin(s): 37  42            Common OE(s):
VCC(s):  9  17  29  41          GND(s): 4  16  24  36
Input Only:  37  38  39  40
Output Only:
Input/Output: 1  2  3  5  6  7  8  10  11  12  13  14  15  18
              19  20  21  22  23  25  26  27  28  30  31  32
              33  34  35  37  42  43  44
_____________________________________________________________
Device Notes:
%%
%PZ3064_plcc44
PZ3064_plcc44 Architecture
Mnemonic: PZ3064_plcc44         Mnemonic: PLCC
Pin Count: 44               Total Product Terms:
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
PHILIPS                       PZ3064-plcc44
_____________________________________________________________
Clock Pin(s): 4  43          Common OE(s):
VCC(s): 3  15  23  35           GND(s): 10  22  30  42
Input Only: 1  2  43  44
Output Only:
Input/Output: 5  6  7  8  9  11  12  13  14  16  17  18  19
              20  21  24  25  26  27  28  29  31  32  33  34
              36  37  38  39  40  41
_____________________________________________________________
Device Notes:
%%
%PZ3064_qfp44
PZ3064_qfp44 Architecture
Mnemonic: PZ3064_qfp44          Mnemonic: QFP
Pin Count: 44               Total Product Terms:
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
PHILIPS                       PZ3064-qfp44
_____________________________________________________________
Clock Pin(s): 37  42            Common OE(s):
VCC(s):  9  17  29  41          GND(s): 4  16  24  36
Input Only:  37  38  39  40
Output Only:
Input/Output: 1  2  3  5  6  7  8  10  11  12  13  14  15  18
              19  20  21  22  23  25  26  27  28  30  31  32
              33  34  35  37  42  43  44
_____________________________________________________________
Device Notes:
%%
%PZ3064_plcc68
PZ3064_plcc68 Architecture
Mnemonic: PZ3064_plcc68         Mnemonic: PLCC
Pin Count: 68               Total Product Terms:
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
PHILIPS                       PZ3064-plcc68
_____________________________________________________________
Clock Pin(s):  1  65  67      Common OE(s):
VCC(s):  3  11  21  31  35  43  53  63
GND(s):  6  16  26  34  38  48  58  66
GCLR:  1
Input Only:  1  2  67  68
Output Only:
Input/Output: 4  5  7  8  9  10  12  13  14  15  17  18  19
              20  22  23  24  25  27  28  29  30  32  33  36
              37  39  40  41  42  44  45  46  47  48  50  51
              52  54  55  56  57  59  60  61  62  64  65
_____________________________________________________________
Device Notes:
%%
%PZ3064_plcc84
PZ3064_plcc84 Architecture
Mnemonic: PZ3032_plcc84         Mnemonic: PLCC
Pin Count: 84               Total Product Terms:
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
PHILIPS                       PZ3064-plcc84
_____________________________________________________________
Clock Pin(s): 4  41  44  83  Common OE(s):
VCC(s): 3  13  26  38  43  53  66  78
GND(s): 7  19  32  42  47  59  72  82
Input Only: 1  2  83  84
Output Only:
Input/Output: 4  5  6  8  9  10  11  12  14  15  16  17  18
              20  21  22  23  24  25  27  28  29  30  31  33
              34  35  36  37  39  40  41  44  45  46  48  49
              50  51  52  54  55  56  57  58  60  61  62  63
              64  65  67  68  69  70  71  73  74  75  76  77
              79  80  81
_____________________________________________________________
Device Notes:
%%
%PZ3064_qfp100
PZ3064_qfp100 Architecture
Mnemonic: PZ3032_qfp100         Mnemonic: QFP
Pin Count: 100              Total Product Terms:
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
PHILIPS                       PZ3064-qfp100
_____________________________________________________________
Clock Pin(s): 39  42  89  94    Common OE(s):
VCC(s): 5  20  36  53  68  84  93
GND(s): 13  28  40  61  76  88  97
Input Only: 89  90  91  92
Output Only:
Input/Output: 1  2  3  4  6  7  8  9  10  11  12  14  15  16
              17  18  19  21  22  23  24  25  26  27  29  30
              31  32  33  34  35  37  38  39  42  43  44  46
              47  48  49  50  51  52  54  55  56  57  58  59
              60  62  63  64  65  66  67  69  70  71  72  73
              74  75  77  78  79  80  81  82  83  85  86  87
              94  95  96  98  99  100
_____________________________________________________________
Device Notes:
%%
%PZ3128_plcc84
PZ3128_plcc84 Architecture
Mnemonic: PZ3128_plcc84         Mnemonic: PLCC
Pin Count: 84               Total Product Terms:
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
PHILIPS                       PZ3128-plcc84
_____________________________________________________________
Clock Pin(s): 4  41  44  83  Common OE(s):
VCC(s): 3  13  26  38  43  53  66  78
GND(s): 7  19  32  42  47  59  72  82
Input Only: 1  2  83  84
Output Only:
Input/Output: 4  5  6  8  9  10  11  12  14  15  16  17  18
              20  21  22  23  24  25  27  28  29  30  31  33
              34  35  36  37  39  40  41  44  45  46  48  49
              50  51  52  54  55  56  57  58  60  61  62  63
              64  65  67  68  69  70  71  73  74  75  76  77
              79  80  81
_____________________________________________________________
Device Notes:
%%
%PZ3128_qfp100
PZ3128_qfp100 Architecture
Mnemonic: PZ3128_qfp100         Mnemonic: QFP
Pin Count: 100              Total Product Terms:
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
PHILIPS                       PZ3128-qfp100
_____________________________________________________________
Clock Pin(s): 39  42  89  94    Common OE(s):
VCC(s): 5  20  36  53  68  84  93
GND(s): 13  28  40  61  76  88  97
Input Only: 89  90  91  92
Output Only:
Input/Output: 1  2  3  4  6  7  8  9  10  11  12  14  15  16
              17  18  19  21  22  23  24  25  26  27  29  30
              31  32  33  34  35  37  38  39  42  43  44  46
              47  48  49  50  51  52  54  55  56  57  58  59
              60  62  63  64  65  66  67  69  70  71  72  73
              74  75  77  78  79  80  81  82  83  85  86  87
              94  95  96  98  99  100
_____________________________________________________________
Device Notes:
%%
%PZ3128_lqf128
PZ3128_lqf128 Architecture
Mnemonic: PZ3128_lqf128         Mnemonic: LQFP
Pin Count: 128              Total Product Terms:
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
PHILIPS                       PZ3128-lqfp128
_____________________________________________________________
Clock Pin(s): 50  53  114  119  Common OE(s):
VCC(s): 7  25  46  52  66  87  108  118
GND(s): 16  37  51  57  78  96  113  123
Input Only: 114  115  116  117
Output Only:
Input/Output: 1  2  3  8  9  10  11  12  13  14  15  17  18
              19  20  21  22  23  24  26  27  28  29  30  31
              32  36  38  39  40  41  42  43  44  45  47  48
              49  50  53  54  55  56  58  59  60  61  62  63
              64  65  67  71  72  73  74  75  76  77  79  80
              81  82  83  84  85  86  88  89  90  91  92  93
              94  95  100  101  102  103  104  105  106  107
              109  110  111  112  119  120  121  122  123  124
              125  126  127  128
N/C: 4  5  6  33  34  35  68  69  70  97  98  99
_____________________________________________________________
Device Notes:
%%
%PZ3128_qfp160
PZ3128_qfp160 Architecture
Mnemonic: PZ3128_qfp160         Mnemonic: QFP
Pin Count: 160              Total Product Terms:
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
PHILIPS                       PZ3128-qfp160
_____________________________________________________________
Clock Pin(s): 59  62  139  144  Common OE(s):
VCC(s): 8  26  55  61  79  104  133  143
GND(s): 17  42  60  66  95  113  138  148
Input Only: 139  140  141  142
Output Only:
Input/Output: 9  10  11  12  13  14  15  16  18  19  20  21
              22  23  24  25  27  28  29  30  31  32  33  41
              43  48  49  50  51  52  53  54  56  57  58  59
              62  63  64  65  67  68  69  70  71  72  73  78
              80  88  89  90  91  92  93  94  96  97  98  99
              100  101  102  103  105  106  107  108  109  110
              111  112  121  122  123  128  129  130  131  132
              134  135  136  137  144  145  146  147  149  150
              151  152  153  158  159  160
N/C: 1  2  3  4  5  6  7  34  35  36  37  38  39  40  44  45
     46  47  74  75  76  77  81  82  83  84  85  86  87  114
     115  116  117  118  119  120  124  125  126  127  154
     155  156  157
_____________________________________________________________
Device Notes:
%%
%PZ5032_plcc44
PZ5032_plcc44 Architecture
Mnemonic: PZ5032_plcc44         Mnemonic: PLCC
Pin Count: 44               Total Product Terms:
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
PHILIPS                       PZ5032-plcc44
_____________________________________________________________
Clock Pin(s): 4  43          Common OE(s):
VCC(s): 3  15  23  35           GND(s): 10  22  30  42
Input Only: 1  2  43  44
Output Only:
Input/Output: 5  6  7  8  9  11  12  13  14  16  17  18  19
              20  21  24  25  26  27  28  29  31  32  33  34
              36  37  38  39  40  41
_____________________________________________________________
Device Notes:
%%
%PZ5032_qfp44
PZ5032_qfp44 Architecture
Mnemonic: PZ5032_qfp44          Mnemonic: QFP
Pin Count: 44               Total Product Terms:
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
PHILIPS                       PZ5032-qfp44
_____________________________________________________________
Clock Pin(s): 37  42            Common OE(s):
VCC(s):  9  17  29  41          GND(s): 4  16  24  36
Input Only:  37  38  39  40
Output Only:
Input/Output: 1  2  3  5  6  7  8  10  11  12  13  14  15  18
              19  20  21  22  23  25  26  27  28  30  31  32
              33  34  35  37  42  43  44
_____________________________________________________________
Device Notes:
%%
%PZ5064_plcc44
PZ5064_plcc44 Architecture
Mnemonic: PZ5064_plcc44         Mnemonic: PLCC
Pin Count: 44               Total Product Terms:
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
PHILIPS                       PZ5064-plcc44
_____________________________________________________________
Clock Pin(s): 4  43          Common OE(s):
VCC(s): 3  15  23  35           GND(s): 10  22  30  42
Input Only: 1  2  43  44
Output Only:
Input/Output: 5  6  7  8  9  11  12  13  14  16  17  18  19
              20  21  24  25  26  27  28  29  31  32  33  34
              36  37  38  39  40  41
_____________________________________________________________
Device Notes:
%%
%PZ5064_qfp44
PZ5064_qfp44 Architecture
Mnemonic: PZ5064_qfp44          Mnemonic: QFP
Pin Count: 44               Total Product Terms:
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
PHILIPS                       PZ5064-qfp44
_____________________________________________________________
Clock Pin(s): 37  42            Common OE(s):
VCC(s):  9  17  29  41          GND(s): 4  16  24  36
Input Only:  37  38  39  40
Output Only:
Input/Output: 1  2  3  5  6  7  8  10  11  12  13  14  15  18
              19  20  21  22  23  25  26  27  28  30  31  32
              33  34  35  37  42  43  44
_____________________________________________________________
Device Notes:
%%
%PZ5064_plcc68
PZ5064_plcc68 Architecture
Mnemonic: PZ5064_plcc68         Mnemonic: PLCC
Pin Count: 68               Total Product Terms:
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
PHILIPS                       PZ5064-plcc68
_____________________________________________________________
Clock Pin(s):  1  65  67      Common OE(s):
VCC(s):  3  11  21  31  35  43  53  63
GND(s):  6  16  26  34  38  48  58  66
GCLR:  1
Input Only:  1  2  67  68
Output Only:
Input/Output: 4  5  7  8  9  10  12  13  14  15  17  18  19
              20  22  23  24  25  27  28  29  30  32  33  36
              37  39  40  41  42  44  45  46  47  48  50  51
              52  54  55  56  57  59  60  61  62  64  65
_____________________________________________________________
Device Notes:
%%
%PZ5064_plcc84
PZ5064_plcc84 Architecture
Mnemonic: PZ5032_plcc84         Mnemonic: PLCC
Pin Count: 84               Total Product Terms:
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
PHILIPS                       PZ5064-plcc84
_____________________________________________________________
Clock Pin(s): 4  41  44  83  Common OE(s):
VCC(s): 3  13  26  38  43  53  66  78
GND(s): 7  19  32  42  47  59  72  82
Input Only: 1  2  83  84
Output Only:
Input/Output: 4  5  6  8  9  10  11  12  14  15  16  17  18
              20  21  22  23  24  25  27  28  29  30  31  33
              34  35  36  37  39  40  41  44  45  46  48  49
              50  51  52  54  55  56  57  58  60  61  62  63
              64  65  67  68  69  70  71  73  74  75  76  77
              79  80  81
_____________________________________________________________
Device Notes:
%%
%PZ5064_qfp100
PZ5064_qfp100 Architecture
Mnemonic: PZ5032_qfp100         Mnemonic: QFP
Pin Count: 100              Total Product Terms:
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
PHILIPS                       PZ5064-qfp100
_____________________________________________________________
Clock Pin(s): 39  42  89  94    Common OE(s):
VCC(s): 5  20  36  53  68  84  93
GND(s): 13  28  40  61  76  88  97
Input Only: 89  90  91  92
Output Only:
Input/Output: 1  2  3  4  6  7  8  9  10  11  12  14  15  16
              17  18  19  21  22  23  24  25  26  27  29  30
              31  32  33  34  35  37  38  39  42  43  44  46
              47  48  49  50  51  52  54  55  56  57  58  59
              60  62  63  64  65  66  67  69  70  71  72  73
              74  75  77  78  79  80  81  82  83  85  86  87
              94  95  96  98  99  100
_____________________________________________________________
Device Notes:
%%
%PZ5128_plcc84
PZ5128_plcc84 Architecture
Mnemonic: PZ5128_plcc84         Mnemonic: PLCC
Pin Count: 84               Total Product Terms:
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
PHILIPS                       PZ5128-plcc84
_____________________________________________________________
Clock Pin(s): 4  41  44  83  Common OE(s):
VCC(s): 3  13  26  38  43  53  66  78
GND(s): 7  19  32  42  47  59  72  82
Input Only: 1  2  83  84
Output Only:
Input/Output: 4  5  6  8  9  10  11  12  14  15  16  17  18
              20  21  22  23  24  25  27  28  29  30  31  33
              34  35  36  37  39  40  41  44  45  46  48  49
              50  51  52  54  55  56  57  58  60  61  62  63
              64  65  67  68  69  70  71  73  74  75  76  77
              79  80  81
_____________________________________________________________
Device Notes:
%%
%PZ5128_qfp100
PZ5128_qfp100 Architecture
Mnemonic: PZ5128_qfp100         Mnemonic: QFP
Pin Count: 100              Total Product Terms:
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
PHILIPS                       PZ5128-qfp100
_____________________________________________________________
Clock Pin(s): 39  42  89  94    Common OE(s):
VCC(s): 5  20  36  53  68  84  93
GND(s): 13  28  40  61  76  88  97
Input Only: 89  90  91  92
Output Only:
Input/Output: 1  2  3  4  6  7  8  9  10  11  12  14  15  16
              17  18  19  21  22  23  24  25  26  27  29  30
              31  32  33  34  35  37  38  39  42  43  44  46
              47  48  49  50  51  52  54  55  56  57  58  59
              60  62  63  64  65  66  67  69  70  71  72  73
              74  75  77  78  79  80  81  82  83  85  86  87
              94  95  96  98  99  100
_____________________________________________________________
Device Notes:
%%
%PZ5128_lqf128
PZ5128_lqf128 Architecture
Mnemonic: PZ5128_lqf128         Mnemonic: LQFP
Pin Count: 128              Total Product Terms:
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
PHILIPS                       PZ5128-lqfp128
_____________________________________________________________
Clock Pin(s): 50  53  114  119  Common OE(s):
VCC(s): 7  25  46  52  66  87  108  118
GND(s): 16  37  51  57  78  96  113  123
Input Only: 114  115  116  117
Output Only:
Input/Output: 1  2  3  8  9  10  11  12  13  14  15  17  18
              19  20  21  22  23  24  26  27  28  29  30  31
              32  36  38  39  40  41  42  43  44  45  47  48
              49  50  53  54  55  56  58  59  60  61  62  63
              64  65  67  71  72  73  74  75  76  77  79  80
              81  82  83  84  85  86  88  89  90  91  92  93
              94  95  100  101  102  103  104  105  106  107
              109  110  111  112  119  120  121  122  123  124
              125  126  127  128
N/C: 4  5  6  33  34  35  68  69  70  97  98  99
_____________________________________________________________
Device Notes:
%%
%PZ5128_qfp160
PZ5128_qfp160 Architecture
Mnemonic: PZ5128_qfp160         Mnemonic: QFP
Pin Count: 160              Total Product Terms:
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
PHILIPS                       PZ5128-qfp160
_____________________________________________________________
Clock Pin(s): 59  62  139  144  Common OE(s):
VCC(s): 8  26  55  61  79  104  133  143
GND(s): 17  42  60  66  95  113  138  148
Input Only: 139  140  141  142
Output Only:
Input/Output: 9  10  11  12  13  14  15  16  18  19  20  21
              22  23  24  25  27  28  29  30  31  32  33  41
              43  48  49  50  51  52  53  54  56  57  58  59
              62  63  64  65  67  68  69  70  71  72  73  78
              80  88  89  90  91  92  93  94  96  97  98  99
              100  101  102  103  105  106  107  108  109  110
              111  112  121  122  123  128  129  130  131  132
              134  135  136  137  144  145  146  147  149  150
              151  152  153  158  159  160
N/C: 1  2  3  4  5  6  7  34  35  36  37  38  39  40  44  45
     46  47  74  75  76  77  81  82  83  84  85  86  87  114
     115  116  117  118  119  120  124  125  126  127  154
     155  156  157
_____________________________________________________________
Device Notes:
%%
%RA10P4
RA10P4 Architecture
Mnemonic: RA10P4              Mnemonic: DIP
Pin Count: 18             Total Product Terms: 1024
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       53/6352
AMD/MMI                       53/6353
AMD/MMI                       AM27S32
AMD/MMI                       AM27S33
HARRIS                        HM7642
HARRIS                        HM7642A
HARRIS                        HM7642B
HARRIS                        HM7643
HARRIS                        HM7643A
HARRIS                        HM7643B
NATIONAL                      DM74S572
NATIONAL                      DM74S572A
NATIONAL                      DM74S573
NATIONAL                      DM74S573A
NATIONAL                      DM74S573B
PHILIPS                       82S137/A/B
TI                            TBP24S41
TI                            TBP24SA41
_____________________________________________________________
%%
%RA10P8
RA10P8 Architecture
Mnemonic: RA10P8              Mnemonic: DIP
Pin Count: 24             Total Product Terms: 1024
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       53/6380
AMD/MMI                       53/6380JS
AMD/MMI                       53/6380S
AMD/MMI                       53/6381
AMD/MMI                       53/6381JS
AMD/MMI                       53/6381S
AMD/MMI                       AM27S180
AMD/MMI                       AM27S181
AMD/MMI                       AM27S37
CYPRESS                       CY7C282
HARRIS                        HM7680
HARRIS                        HM7680P
HARRIS                        HM7680R
HARRIS                        HM7680RP
HARRIS                        HM7681
HARRIS                        HM7681A
HARRIS                        HM7681P
HARRIS                        HM7681R
HARRIS                        HM7681RP
NATIONAL                      DM87S180
NATIONAL                      DM87S181
NATIONAL                      DM87S181A
PHILIPS                       82S180
PHILIPS                       82S181/A/B
TI                            TBP28S86A
TI                            TBP28SA86A
_____________________________________________________________
Device Notes:
1.  Active-HI chip enables are simulated as Active-LO.
%%
%RA11P4
RA11P4 Architecture
Mnemonic: RA11P4              Mnemonic: DIP
Pin Count: 18             Total Product Terms: 2048
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       53/6388
AMD/MMI                       53/6389
AMD/MMI                       AM27S184
AMD/MMI                       AM27S185
HARRIS                        HM7684
HARRIS                        HM7684P
HARRIS                        HM7685
HARRIS                        HM7685A
HARRIS                        HM7685P
NATIONAL                      DM87S184
NATIONAL                      DM87S185
NATIONAL                      DM87S185A
NATIONAL                      DM87S185B
PHILIPS                       82S184
PHILIPS                       82S185/A/B
TI                            TBP24S81
TI                            TBP24SA81
_____________________________________________________________
%%
%RA11P8
RA11P8 Architecture
Mnemonic: RA11P8              Mnemonic: DIP
Pin Count: 24             Total Product Terms: 2048
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       53/63S1681
AMD/MMI                       53/63S1681A
AMD/MMI                       AM27S190
AMD/MMI                       AM27S191
CYPRESS                       CY7C292
HARRIS                        HM76160
HARRIS                        HM76161
HARRIS                        HM76161A
HARRIS                        HM76161B
NATIONAL                      DM87S190
NATIONAL                      DM87S190A
NATIONAL                      DM87S190B
NATIONAL                      DM87S191
NATIONAL                      DM87S191A
NATIONAL                      DM87S191B
PHILIPS                       82S191/A/B/C
TI                            TBP24SA166
TI                            TBP28S166
TI                            TBP28SA166
_____________________________________________________________
Device Notes:
1.  Active-HI chip enables are simulated as Active-LO.
%%
%RA12P4
RA12P4 Architecture
Mnemonic: RA12P4              Mnemonic: DIP
Pin Count: 20             Total Product Terms: 4096
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       53/63S1641
AMD/MMI                       53/63S1641A
AMD/MMI                       AM27S40
AMD/MMI                       AM27S41
HARRIS                        HM76164
HARRIS                        HM76165
NATIONAL                      DM87S195
NATIONAL                      DM87S195A
NATIONAL                      DM87S195B
PHILIPS                       82S195
_____________________________________________________________
%%
%RA12P8
RA12P8 Architecture
Mnemonic: RA12P8              Mnemonic: DIP
Pin Count: 24             Total Product Terms: 4096
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       53/63S3281
AMD/MMI                       53/63S3281A
AMD/MMI                       AM27S43
HARRIS                        HM76321
NATIONAL                      DM87S321
NATIONAL                      DM87S321A
PHILIPS                       82S321
TI                            TBP24S166
_____________________________________________________________
Device Notes:
1.  Active-HI chip enables are simulated as Active-LO.
%%
%RA13P8
RA13P8 Architecture
Mnemonic: RA13P8              Mnemonic: DIP
Pin Count: 24             Total Product Terms: 8192
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       AM27S49
CYPRESS                       CY7C264
HARRIS                        HM76641
HARRIS                        HM76641A
PHILIPS                       82S641
_____________________________________________________________
%%
%RA5P8
RA5P8 Architecture
Mnemonic: RA5P8               Mnemonic: DIP
Pin Count: 16             Total Product Terms:   32
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       53/6330
AMD/MMI                       53/6331
AMD/MMI                       AM27S18
AMD/MMI                       AM27S19
HARRIS                        HM7602
HARRIS                        HM7603
NATIONAL                      DM74S188
NATIONAL                      DM74S288
PHILIPS                       82S123/A
PHILIPS                       82S23/A
TI                            TBP18S030
TI                            TBP18SA030
_____________________________________________________________
%%
%RA8P4
RA8P4 Architecture
Mnemonic: RA8P4               Mnemonic: DIP
Pin Count: 16             Total Product Terms:  256
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       53/6300
AMD/MMI                       53/6301
AMD/MMI                       AM27S20
AMD/MMI                       AM27S21
HARRIS                        HM7610
HARRIS                        HM7610A
HARRIS                        HM7610B
HARRIS                        HM7611
HARRIS                        HM7611A
HARRIS                        HM7611B
NATIONAL                      DM74S287
NATIONAL                      DM74S387
PHILIPS                       82S126/A
PHILIPS                       82S129/A
TI                            TBP24S10
TI                            TBP24SA10
_____________________________________________________________
%%
%RA8P8
RA8P8 Architecture
Mnemonic: RA8P8               Mnemonic: DIP
Pin Count: 20             Total Product Terms:  256
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       53/6308
AMD/MMI                       53/6309
NATIONAL                      DM74LS471
PHILIPS                       82S135
TI                            TBP18S22
TI                            TBP18SA22
_____________________________________________________________
%%
%RA9P4
RA9P4 Architecture
Mnemonic: RA9P4               Mnemonic: DIP
Pin Count: 16             Total Product Terms:  256
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       53/6305
AMD/MMI                       53/6306
AMD/MMI                       AM27S12
AMD/MMI                       AM27S13
HARRIS                        HM7620
HARRIS                        HM7620A
HARRIS                        HM7620B
HARRIS                        HM7621
HARRIS                        HM7621A
HARRIS                        HM7621B
NATIONAL                      DM74S570
NATIONAL                      DM74S570A
NATIONAL                      DM74S571
NATIONAL                      DM74S571A
NATIONAL                      DM74S571B
PHILIPS                       82S130/A
PHILIPS                       82S131/A
_____________________________________________________________
%%
%RA9P8
RA9P8 Architecture
Mnemonic: RA9P8               Mnemonic: DIP
Pin Count: 20             Total Product Terms:  512
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
AMD/MMI                       53/6348
AMD/MMI                       53/6349
AMD/MMI                       AM27S28
AMD/MMI                       AM27S29
HARRIS                        HM7648
HARRIS                        HM7649
HARRIS                        HM7649A
_____________________________________________________________
%%
%V2500
V2500 Architecture
Mnemonic: V2500               Mnemonic: DIP
Pin Count: 40             Total Product Terms:  416
Extensions: D AR CK OE SP IO
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
ATMEL                         ATV2500H/L
ATMEL                         ATV2500LV/LVL
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s): 10                    GND(s): 30
Input Only: 1  2  3  17  18  19  20  21  22  23  37  38  39
            40
Output Only:
Input/Output:  4   5   6   7   8   9  11  12  13  14  15  16
              24  25  26  27  28  29  31  32  33  34  35  36
Q2 REG Node:  41  42  43  44  45  46  47  48  49  50  51  52
              53  54  55  56  57  58  59  60  61  62  63  64
Q1 REG Node:  65  66  67  68  69  70  71  72  73  74  75  76
              77  78  79  80  81  82  83  84  85  86  87  88
%%
%V2500lcc
V2500lcc Architecture
Mnemonic: V2500lcc            Mnemonic: PLCC
Pin Count: 44             Total Product Terms:  416
Extensions: D AR CK OE SP IO
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
ATMEL                         ATV2500H/L
ATMEL                         ATV2500LV/LVL
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s): 10                    GND(s): 30
Input Only: 1  2  3  17  18  19  20  21  22  23  37  38  39
            40
Output Only:
Input/Output:  4   5   6   7   8   9  11  12  13  14  15  16
              24  25  26  27  28  29  31  32  33  34  35  36
Q2 REG Node:  41  42  43  44  45  46  47  48  49  50  51  52
              53  54  55  56  57  58  59  60  61  62  63  64
Q1 REG Node:  65  66  67  68  69  70  71  72  73  74  75  76
              77  78  79  80  81  82  83  84  85  86  87  88
%%
%V2500B
V2500B Architecture
Mnemonic: V2500B              PLCC Mnemonic: DIP
Pin Count: 40             Total Product Terms:  416
Extensions: D T AR CK OE SP IO CE
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
ATMEL                         ATV2500B/L
_____________________________________________________________
Clock Pin(s): 1               Common OE(s):
VCC(s): 10                    GND(s): 30
Input Only: 1  2  3  17  18  19  20  21  22  23  37  38  39
            40
Output Only:
Input/Output:  4   5   6   7   8   9  11  12  13  14  15  16
              24  25  26  27  28  29  31  32  33  34  35  36
Q2 REG Node:  41  42  43  44  45  46  47  48  49  50  51  52
              53  54  55  56  57  58  59  60  61  62  63  64
Q1 REG Node:  65  66  67  68  69  70  71  72  73  74  75  76
              77  78  79  80  81  82  83  84  85  86  87  88
_____________________________________________________________
Device Notes:
1. Clock Assignment
    Asynchronous clock - use the .CK extension
        Ex. X.CK = A & B & C;
    Synchronous clock - use the .CE extension
        Ex. X.CE = 'b'1;
        Set the Clock enable term to 'b'1 to allow the use
        of pin 1 to be the clock signal.
    Gated synchronous clock- use the .CE extension
        Ex. X.CE = A & B & C;
        The Clock pin (pin 1) will be gated by the
        (A & B & C) function.
%%
%V2500Blcc
V2500Blcc Architecture
Mnemonic: V2500Blcc           PLCC Mnemonic: PLCC
Pin Count: 44             Total Product Terms:  416
Extensions: D T AR CK OE SP IO CE
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
ATMEL                         ATV2500B/L
_____________________________________________________________
Clock Pin(s): 1               Common OE(s):
VCC(s): 10                    GND(s): 30
Input Only: 1  2  3  17  18  19  20  21  22  23  37  38  39
            40
Output Only:
Input/Output:  4   5   6   7   8   9  11  12  13  14  15  16
              24  25  26  27  28  29  31  32  33  34  35  36
Q2 REG Node:  41  42  43  44  45  46  47  48  49  50  51  52
              53  54  55  56  57  58  59  60  61  62  63  64
Q1 REG Node:  65  66  67  68  69  70  71  72  73  74  75  76
              77  78  79  80  81  82  83  84  85  86  87  88
_____________________________________________________________
Device Notes:
1. Clock Assignment
    Asynchronous clock - use the .CK extension
        Ex. X.CK = A & B & C;
    Synchronous clock - use the .CE extension
        Ex. X.CE = 'b'1;
        Set the Clock enable term to 'b'1 to allow the use
        of pin 1 to be the clock signal.
    Gated synchronous clock- use the .CE extension
        Ex. X.CE = A & B & C;
        The Clock pin (pin 1) will be gated by the
        (A & B & C) function.
%%
%V5000
V5000 Architecture
Mnemonic: V5000               Mnemonic: DIP
Pin Count: 68             Total Product Terms:  1232
Extensions: D T AR CK OE AP IO CE IOL LQ
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
ATMEL                         ATV5000/L
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s): 3  20  37  54         GND(s): 16  33  50  67
Input Only: 1  2  32  34  35  36  66  68
Output Only:
Input/Output: 4  5  6  7  8  9  10  11  12  13  14  15  17
              18  19  21  22  23  24  25  26  27  28  29  30
              31  38  39  40  41  42  43  44  45  46  47  48
              49  51  52  53  55  56  57  58  60  61  62  63
              64  65
%%
%V750
V750 Architecture
Mnemonic: V750                Mnemonic: DIP
Pin Count: 24             Total Product Terms:  171
Extensions: D AR CK OE SP DFB IO
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
ATMEL                         ATV750/L
ATMEL                         ATV750LV/LVL
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s): 24                    GND(s): 12
Input Only: 1  2  3  4  5  6  7  8  9  10  11  13
Output Only:
Input/Output: 14  15  16  17  18  19  20  21  22  23
Q1 REG nodes: 25  26  27  28  29  30  31  32  33  34
Q0 REG nodes: 35  36  37  38  39  40  41  42  43  44
%%
%V750lcc
V750lcc Architecture
Mnemonic: V750lcc             Mnemonic: PLCC
Pin Count: 28             Total Product Terms:  171
Extensions: D AR CK OE SP DFB IO
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
ATMEL                         ATV750/L
ATMEL                         ATV750LV/LVL
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s): 24                    GND(s): 12
Input Only: 1  2  3  4  5  6  7  8  9  10  11  13
Output Only:
Input/Output: 14  15  16  17  18  19  20  21  22  23
Q1 REG nodes: 25  26  27  28  29  30  31  32  33  34
Q0 REG nodes: 35  36  37  38  39  40  41  42  43  44
%%
%V750B
V750B Architecture
Mnemonic: V750B               PLCC Mnemonic: DIP
Pin Count: 24             Total Product Terms:  171
Extensions: D T AR CK CKMUX OE SP DFB IO
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
ATMEL                         ATV750B/L
_____________________________________________________________
Clock Pin(s): 1               Common OE(s):
VCC(s): 24                    GND(s): 12
Input Only: 1  2  3  4  5  6  7  8  9  10  11  13
Output Only:
Input/Output: 14  15  16  17  18  19  20  21  22  23
Q1 REG nodes: 25  26  27  28  29  30  31  32  33  34
Q0 REG nodes: 35  36  37  38  39  40  41  42  43  44
_____________________________________________________________
Device Notes:
1. Clock Assignment
    Asynchronous clock - use the .CK extension
        Ex. X.CK = A & B & C;
    Synchronous clock - use the .CKMUX extension
        Ex. X.CKMUX = 'b'1;
%%
%V750Blcc
V750Blcc Architecture
Mnemonic: V750Blcc            PLCC Mnemonic: PLCC
Pin Count: 28             Total Product Terms:  171
Extensions: D T AR CK CKMUX OE SP DFB IO
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
ATMEL                         ATV750B/L
_____________________________________________________________
Clock Pin(s): 1               Common OE(s):
VCC(s): 24                    GND(s): 12
Input Only: 1  2  3  4  5  6  7  8  9  10  11  13
Output Only:
Input/Output: 14  15  16  17  18  19  20  21  22  23
Q1 REG nodes: 25  26  27  28  29  30  31  32  33  34
Q0 REG nodes: 35  36  37  38  39  40  41  42  43  44
_____________________________________________________________
Device Notes:
1. Clock Assignment
    Asynchronous clock - use the .CK extension
        Ex. X.CK = A & B & C;
    Synchronous clock - use the .CKMUX extension
        Ex. X.CKMUX = 'b'1;
%%
%XC7236PC44
XC7236PC44 Architecture
Mnemonic: XC7236PC44          Mnemonic: PLCC
Pin Count: 44             Total Product Terms: 99999
Extensions: D DQ AP AR CK CKMUX OE OEMUX L LQ LEMUX IOD IOL
            IOCK
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
XILINX                        XC7236
_____________________________________________________________
Clock Pin(s): 9  10  11       Common OE(s): 32
VCC(s): 1  12  23  34         GND(s): 7  17  29  39
Input Only: 3  4
Output Only: 9  10  11  32
Input/Output:2  5  6  8  13  14  15  16  18  19  20  21  22
             24  25  26  27  28  30  31  33  35  36  37  38
             40  41  42  43  44
%%
%XC7236APC44
XC7236APC44 Architecture
Mnemonic: XC7236APC44         Mnemonic: PLCC
Pin Count: 44             Total Product Terms: 99999
Extensions: D DQ AP AR CK CKMUX OE OEMUX L LQ LEMUX IOD IOL
            IOCK
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
XILINX                        XC7236A
_____________________________________________________________
Clock Pin(s): 9  10  11       Common OE(s): 32
VCC(s): 1  12  23  34         GND(s):7  17  29  39
Input Only: 3  4
Output Only: 9  10  11  32
Input/Output: 2  5  6  8  13  14  15  16  18  19  20  21  22
              24  25  26  27  28  30  31  33  35  36  37  38
              40  41  42  43  44
%%
%XC7272APC68
XC7272APC68 Architecture
Mnemonic: XC7272APC68         Mnemonic: PLCC
Pin Count: 68             Total Product Terms: 99999
Extensions: D DQ AP AR CK CKMUX OE L LQ LEMUX IOD IOL IOCK
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
XILINX                        XC7272
_____________________________________________________________
Clock Pin(s): 7  8            Common OE(s):
VCC(s): 16  35  54            GND(s): 6  15  21  31  39  49
                                      59  64
Input Only: 2  3  4  5  65  66  67  68
Output Only: 7  8  11  12  13  14  55  56  57  58
Input/Output: 9  10  17  18  19  20  22  23  24  25  26  27
              28  29  30  32  33  34  36  37  38  40  41  42
              43  44  45  46  47  48  50  51  52  53  55  56
              57  58  60  61  62  63
%%
%XC7272APC84
XC7272APC84 Architecture
Mnemonic: XC7272APC84         Mnemonic: PLCC
Pin Count: 84             Total Product Terms: 99999
Extensions: D DQ AP AR CK CKMUX OE L LQ LEMUX IOD IOL IOCK
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
XILINX                        XC7272 (PLCC)
_____________________________________________________________
Clock Pin(s): 9  10           Common OE(s):
VCC(s): 22  43  64            GND(s): 8  17  27  37  49  59
                                      69  78
Input Only: 2  3  4  5  6  7  79  80  81  82  83  84
Output Only: 9  10  13  14  15  16  18  19  20  21  65  66
             67  68  70  71  72  73
Input/Output: 11  12  23  24  25  26  28  29  30  31  32  33
              34  35  36  38  39  40  41  42  44  45  46  47
              48  50  51  52  53  54  55  56  57  58  60  61
              62  63  74  75  76  77
%%
%XC7272APG84
XC7272APG84 Architecture
Mnemonic: XC7272APG84         Mnemonic: PGA
Pin Count: 84             Total Product Terms: 99999
Extensions: D DQ AP AR CK CKMUX OE L LQ LEMUX IOD IOL IOCK
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
XILINX                        XC7272 (PGA)
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
%%
%XC7272APC68
XC7272PC68 Architecture
Mnemonic: XC7272PC68          Mnemonic: PLCC
Pin Count: 68             Total Product Terms: 99999
Extensions: D DQ AP AR CK CKMUX OE L LQ LEMUX IOD IOL IOCK
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
XILINX                        XC7272A
_____________________________________________________________
Clock Pin(s): 7  8            Common OE(s):
VCC(s): 16  35  54            GND(s): 6  15  21  31  39  49
                                      59  64
Input Only: 2  3  4  5  65  66  67  68
Output Only: 7  8  11  12  13  14  55  56  57  58
Input/Output: 9  10  17  18  19  20  22  23  24  25  26  27
              28  29  30  32  33  34  36  37  38  40  41  42
              43  44  45  46  47  48  50  51  52  53  55  56
              57  58  60  61  62  63
%%
%XC7272PC84
XC7272PC84 Architecture
Mnemonic: XC7272PC84          Mnemonic: PLCC
Pin Count: 84             Total Product Terms: 99999
Extensions: D DQ AP AR CK CKMUX OE L LQ LEMUX IOD IOL IOCK
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
XILINX                        XC7272A (PLCC)
_____________________________________________________________
Clock Pin(s): 9  10           Common OE(s):
VCC(s): 22  43  64            GND(s): 8  17  27  37  49  59
                                      69  78
Input Only: 2  3  4  5  6  7  79  80  81  82  83  84
Output Only: 9  10  13  14  15  16  18  19  20  21  65  66
             67  68  70  71  72  73
Input/Output: 11  12  23  24  25  26  28  29  30  31  32  33
              34  35  36  38  39  40  41  42  44  45  46  47
              48  50  51  52  53  54  55  56  57  58  60  61
              62  63  74  75  76  77
%%
%XC7272PG84
XC7272PG84 Architecture
Mnemonic: XC7272PG84          Mnemonic: PGA
Pin Count: 84             Total Product Terms: 99999
Extensions: D DQ AP AR CK CKMUX OE L LQ LEMUX IOD IOL IOCK
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
XILINX                        XC7272A (PGA)
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
%%
%XC73108BG225
XC73108BG225 Architecture
Mnemonic: XC73108BG225        Mnemonic: BGA
Pin Count: 225            Total Product Terms: 99999
Extensions: D DQ AP AR CK CKMUX OE OEMUX L LQ LEMUX IOD IOL
            IOCK
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
XILINX                        XC73108 (BGA)
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
%%
%XC73108PC84
XC73108PC84 Architecture
Mnemonic: XC73108PC84         Mnemonic: PLCC
Pin Count: 144            Total Product Terms: 99999
Extensions: D DQ AP AR CK CKMUX OE OEMUX L LQ LEMUX IOD IOL
            IOCK
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
XILINX                        XC73108 (PGA)
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
%%
%XC73108PG144
XC73108PG144 Architecture
Mnemonic: XC73108PG144        Mnemonic: PGA
Pin Count: 144            Total Product Terms: 99999
Extensions: D DQ AP AR CK CKMUX OE OEMUX L LQ LEMUX IOD IOL
            IOCK
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
XILINX                        XC73108 (PGA)
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
%%
%XC73108PQ100
XC73108PQ100 Architecture
Mnemonic: XC73108PQ100        Mnemonic: PQFP
Pin Count: 100            Total Product Terms: 99999
Extensions: D DQ AP AR CK CKMUX OE OEMUX L LQ LEMUX IOD IOL
            IOCK
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
XILINX                        XC73108 (PQFP)
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
%%
%XC73108PQ160
XC73108PQ160 Architecture
Mnemonic: XC73108PQ160        Mnemonic: PQFP
Pin Count: 160            Total Product Terms: 99999
Extensions: D DQ AP AR CK CKMUX OE OEMUX L LQ LEMUX IOD IOL
            IOCK
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
XILINX                        XC73108 (PQFP)
_____________________________________________________________
Clock Pin(s): 33  35  42      Common OE(s): 6 8
VCC(s): 1  10  41  46  61  81 GND(s): 20  31  40  51  70  80
        94  121  141  157             99  100  110  120  127
                                      137
Input Only: 11  13  15  17  18  19  22  23  24  26  28  30
Output Only: 2  4  6  7  8  9  25  27  33  34  35  36  42
             44  47  49  54  56  58  59  60  142  143  144
             145  146  148  152  154  156
Input/Output: 12  14  16  29  32  37  43  45  48  50  55  57
              62  63  64  67  68  69  71  72  73  74  75  76
              77  78  79  82  84  86  87  88  89  90  91  92
              93  95  96  97  98  101  102  103  104  105
              106  107  108  109  111  112  113  114  115
              116  117  122  123  124  125  126  128  129
              130  133  134  135  136  138  139  140  145
              147  151  153  155  158
%%
%XC7318PC44
XC7318PC44 Architecture
Mnemonic: XC7318PC44          Mnemonic: PLCC
Pin Count: 44             Total Product Terms: 99999
Extensions: D DQ T AP AR CKMUX OEMUX
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
XILINX                        XC7318 (PLCC)
_____________________________________________________________
Clock Pin(s): 6  40           Common OE(s): 5
VCC(s): 21  32  41            GND(s): 10  22  31
Input Only: 1  2  3  4  17  18  19  20  22  24  25  26  27
            28  42  43  44
Output Only: 39
Input/Output: 7  8  9  11  12  13  14  15  16  29  30  33
              34  35  36  37  38
%%
%XC7318PQ44
XC7318PQ44 Architecture
Mnemonic: XC7318PQ44          Mnemonic: PQFP
Pin Count: 44             Total Product Terms: 99999
Extensions: D DQ T AP AR CKMUX OEMUX
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
XILINX                        XC7318 (PQFP)
_____________________________________________________________
Clock Pin(s): 6  40           Common OE(s): 5
VCC(s): 21  32  41            GND(s): 10  22  31
Input Only: 1  2  3  4  17  18  19  20  22  24  25  26  27
            28  42  43  44
Output Only: 39
Input/Output: 7  8  9  11  12  13  14  15  16  29  30  33
              34  35  36  37  38
%%
%XC7336PC44
XC7336PC44 Architecture
Mnemonic: XC7336PC44          Mnemonic: PLCC
Pin Count: 44             Total Product Terms: 99999
Extensions: D DQ T AP AR CKMUX OEMUX
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
XILINX                        XC7336 (PLCC)
_____________________________________________________________
Clock Pin(s): 5  6            Common OE(s): 39  40
VCC(s): 21  32  41            GND(s): 10  23  31
Input Only: 28  42
Output Only: 5  6  39  40
Input/Output: 1  2  3  4  7  8  9  11  12  13  14  15  16
              17  18  19  20  22  24  25  26  27  29  30  33
              34  35  36  37  38  43  44
%%
%XC7336PQ44
XC7336PQ44 Architecture
Mnemonic: XC7336PQ44          Mnemonic: PQFP
Pin Count: 44             Total Product Terms: 99999
Extensions: D DQ T AP AR CKMUX OEMUX
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
XILINX                        XC7336 (PQFP)
_____________________________________________________________
Clock Pin(s): 5  6            Common OE(s): 39  40
VCC(s): 21  32  41            GND(s): 10  23  31
Input Only: 28  42
Output Only: 5  6  39  40
Input/Output: 1  2  3  4  7  8  9  11  12  13  14  15  16
              17  18  19  20  22  24  25  26  27  29  30  33
              34  35  36  37  38  43  44
%%
%XC7354PC44
XC7354PC44 Architecture
Mnemonic: XC7354PC44          Mnemonic: PLCC
Pin Count: 44             Total Product Terms: 99999
Extensions: D DQ AP AR CK CKMUX OE OEMUX L LQ LEMUX IOD IOL
            IOCK
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
XILINX                        XC7354
_____________________________________________________________
Clock Pin(s): 5  6            Common OE(s): 40
VCC(s): 21  32  41            GND(s): 10  23  31
Input Only: 1  2  3  4  7  28  42  43  44
Output Only: 5  6  39  40
Input/Output: 8  9  11  12  13  14  15  16  17  18  19  20
              22  24  25  26  27  29  30  33  34  35  36  37
              38
%%
%XC7354PC68
XC7354PC68 Architecture
Mnemonic: XC7354PC68          Mnemonic: PLCC
Pin Count: 68             Total Product Terms: 99999
Extensions: D DQ AP AR CK CKMUX OE OEMUX L LQ LEMUX IOD IOL
            IOCK
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
XILINX                        XC7354
_____________________________________________________________
Clock Pin(s): 8  9  10        Common OE(s): 62  64
VCC(s): 20  30  50  59  63    GND(s): 7  14  34  41  49
Input Only: 1  2  3  5  11  43  65  67  68
Output Only: 8  9  10  60  61  62  64
Input/Output: 4  6  12  13  15  16  17  18  19  21  22  23
              24  25  26  27  28  29  31  32  33  35  36  37
              38  39  40  42  44  45  46  47  48  51  52  53
              54  55  56  57  58  66
%%
%XC7372PC68
XC7372PC68 Architecture
Mnemonic: XC7372PC68          Mnemonic: PLCC
Pin Count: 68             Total Product Terms: 99999
Extensions: D DQ AP AR CK CKMUX OE OEMUX L LQ LEMUX IOD IOL
            IOCK
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
XILINX                        XC7372
_____________________________________________________________
Clock Pin(s): 8  9  10        Common OE(s): 62
VCC(s): 20  30  50  59  63    GND(s): 7  14  34  41  49
Input Only: 2  3  4  5  6  64  65  66  67  68
Output Only: 8  9  10  11  12  13  15  16  17  18  19  51
             52  53  54  55  56  57  58  60  61  62
Input/Output: 21  22  23  24  25  26  27  28  29  31  32  33
              35  36  37  38  39  40  42  43  44  45  46  47
              48
%%
%XC7372PC84
XC7372PC84 Architecture
Mnemonic: XC7372PC84          Mnemonic: PLCC
Pin Count: 84             Total Product Terms: 99999
Extensions: D DQ AP AR CK CKMUX OE OEMUX L LQ LEMUX IOD IOL
            IOCK
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
XILINX                        XC7372
_____________________________________________________________
Clock Pin(s): 9  10  12       Common OE(s): 76  77
VCC(s): 22  38  64  73  78    GND(s): 8  16  27  42  49  60
Input Only: 2  3  4  5  6  7  79  80  81  82  83  84
Output Only: 9  10  12  13  14  15  17  18  19  20  21  65
             66  67  68  69  70  71  72  74  75  76  77
Input/Output: 11  23  24  25  26  28  29  30  31  32  33  34
              35  36  37  39  40  41  43  44  45  46  47  48
              50  51  52  53  54  55  56  57  58  59  61  62
              63
%%
%XC73108PC84
XC73108PC84 Architecture
Mnemonic: XC73108PC84         Mnemonic: PLCC
Pin Count: 84             Total Product Terms: 99999
Extensions: D DQ AP AR CK CKMUX OE OEMUX L LQ LEMUX IOD IOL
            IOCK
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
XILINX                        XC73108 (PLCC)
_____________________________________________________________
Clock Pin(s): 9  10  12       Common OE(s): 76  77
VCC(s): 22  38  64  73  78    GND(s): 8  16  27  42  49  60
Input Only: 2  3  4  5  6  7  79  80  81  82  83  84
Output Only: 9  10  12  13  14  15  17  18  19  20  21  65
             66  67  68  69  70  71  72  74  75  76  77
Input/Output: 11  23  24  25  26  28  30  31  32  33  34  35
              36  37  39  40  41  43  44  45  46  47  48  50
              51  52  53  54  55  56  57  58  59  61  62  63
%%
%XILINX
XILINX Architecture
Mnemonic: XILINX              Mnemonic:
Pin Count: 200            Total Product Terms: 99999
Extensions:
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
XILINX                        none
_____________________________________________________________
Clock Pin(s):                 Common OE(s):
VCC(s):                       GND(s):
Input Only:
Output Only:
Input/Output:
_____________________________________________________________
Device Notes:
1.  This mnemonic is used to produce a PDS file with some
    specific Xilinx syntax. This allows a designer to
    automatically translate the PDS file with the PDS2XNF
    translator. ( A more advanced way of supporting the
    Xilinx devices is available, please see the following
    mnemonics: GA2000, GA3000, GA4000 ).
%%
%XC9536PC44
XC9536PC44 Architecture
Mnemonic: XC9536PC44          Mnemonic: PLCC
Pin Count: 44             Total Product Terms: 99999
Extensions: D DQ AP AR CK CKMUX OE OEMUX L LQ LEMUX IOD IOL
            IOCK
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
XILINX                        XC9536(F)-(speed)PC44C
XILINX                        XC9536(F)-(speed)PC44I
_____________________________________________________________
Clock Pin(s): 5  6  7         Common OE(s):
VCC(s): 21  41  32            GND(s):23  10  31
Input Only:
Output Only:
Input/Output: 1  2  3  4  5  6  7  8  9  11  12  13  14  18
              19  20  22  24  25  26  27  28  29  33  34  35
              36  37  38  39  40  42  43  44
ISP Only: 15  16  17  30
%%
%XC9536VQ44
XC9536VQ44 Architecture
Mnemonic: XC9536VQ44         Mnemonic: TQFP
Pin Count: 44             Total Product Terms: 99999
Extensions: D DQ AP AR CK CKMUX OE L LQ LEMUX IOD IOL IOCK
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
XILINX                        XC9536(F)-(speed)VQ44C
XILINX                        XC9536(F)-(speed)VQ44I
_____________________________________________________________
Clock Pin(s): 1  43  44       Common OE(s):
VCC(s): 15  35  26            GND(s):4  17  25
Input Only:
Output Only:
Input/Output: 1  2  3  5  6  7  8  12  13  14  16  18  19  20
              21  22  23  27  28  29  30  31  32  33  34  36
              37  38  39  40  41  42  43  44
ISP Only: 11  9  24  10
%%
%XC9572PC44
XC9572PC44 Architecture
Mnemonic: XC9572PC44          Mnemonic: PLCC
Pin Count: 44             Total Product Terms: 99999
Extensions: D DQ AP AR CK CKMUX OE OEMUX L LQ LEMUX IOD IOL
            IOCK
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
XILINX                        XC9572(F)-(speed)PC44C
XILINX                        XC9572(F)-(speed)PC44I
_____________________________________________________________
Clock Pin(s): 5  6  7         Common OE(s):
VCC(s): 21  41  32            GND(s):23  10  31
Input Only:
Output Only:
Input/Output: 1  2  3  4  5  6  7  8  9  11  12  13  14  18
              19  20  22  24  25  26  27  28  29  33  34  35
              36  37  38  39  40  42  43  44
ISP Only: 15  16  17  30
%%
%XC9572PC84
XC9572PC84 Architecture
Mnemonic: XC9572PC84          Mnemonic: PLCC
Pin Count: 84             Total Product Terms: 99999
Extensions: D DQ AP AR CK CKMUX OE OEMUX L LQ LEMUX IOD IOL
            IOCK
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
XILINX                        XC9572(F)-(speed)PC84C
XILINX                        XC9572(F)-(speed)PC84I
_____________________________________________________________
Clock Pin(s): 9  10  12       Common OE(s):
VCC(s): 38  73  78  22  64    GND(s): 8  16  27  42  49  60
Input Only:
Output Only:
Input/Output: 1  2  3  4  5  6  7  9  11  13  14  15  17  18
              19  20  21  23  24  25  26  31  32  33  34  35
              36  37  39  40  41  43  44  45  46  47  48  50
              51  52  53  54  55  56  57  58  61  62  63  65
              66  67  68  69  70  71  72  74  75  76  77  79
              80  81  82  83  84
ISP Only: 28  29  30  59
%%
%XC9572PQ100
XC9572PQ100 Architecture
Mnemonic: XC9572PQ100         Mnemonic: PQFP
Pin Count: 100            Total Product Terms: 99999
Extensions: D DQ AP AR CK CKMUX OE OEMUX L LQ LEMUX IOD IOL
            IOCK
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
XILINX                        XC9572(F)-(speed)PQ100C
XILINX                        XC9572(F)-(speed)PQ100C
_____________________________________________________________
Clock Pin(s): 24  25  29      Common OE(s):
VCC(s): 7  28  40  53  59  90  100
GND(s): 2  23  33  46  64  71  77  86
Input Only:
Output Only:
Input/Output: 1  3  5  6  8  10  11  12  13  14  15  16  17
              18  19  20  22  24  25  27  29  30  31  32  34
              35  37  38  39  41  42  43  44  51  52  54  55
              56  57  58  60  61  62  63  65  66  67  68  69
              70  72  73  74  76  78  79  80  81  83  84  87
              88  89  91  92  93  94  95  96  97  98  99
ISP Only: 50  47  85  49
N/C:  4  9  21  26  36  45  48  75  82
%%
%XC95108PC84
XC95108PC84 Architecture
Mnemonic: XC95108PC84         Mnemonic: PLCC
Pin Count: 84             Total Product Terms: 99999
Extensions: D DQ AP AR CK CKMUX OE OEMUX L LQ LEMUX IOD IOL
            IOCK
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
XILINX                        XC95108(F)-(speed)PC84C
XILINX                        XC95108(F)-(speed)PC84I
_____________________________________________________________
Clock Pin(s): 9  10  12       Common OE(s):
VCC(s): 38  73  78  22  64    GND(s): 8  16  27  42  49  60
Input Only:
Output Only:
Input/Output: 1  2  3  4  5  6  7  9  10  11  13  14  15  17
              18  19  20  21  23  24  25  26  31  32  33  34
              35  36  37  39  40  41  43  44  45  46  47  48
              50  51  52  53  54  55  56  57  58  61  62  63
              65  66  67  68  69  70  71  72  74  75  76  77
              79  80  81  82  83  84
ISP Only: 28  29  30  59
%%
%XC95108PQ100
XC95108PQ100 Architecture
Mnemonic: XC95108PQ100        Mnemonic: PQFP
Pin Count: 100            Total Product Terms: 99999
Extensions: D DQ AP AR CK CKMUX OE OEMUX L LQ LEMUX IOD IOL
            IOCK
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
XILINX                        XC95108(F)-(speed)PQ100C
XILINX                        XC95108(F)-(speed)PQ100I
_____________________________________________________________
Clock Pin(s): 24  25  29      Common OE(s):
VCC(s): 7  28  40  53  59  90  100
GND(s): 2  23  33  46  64  71  77  86
Input Only:
Output Only:
Input/Output: 1  3  4  5  6  8  9  10  11  12  13  14  15
              16  17  18  19  20  21  22  24  25  26  27
              29  30  31  32  34  35  36  37  38  39  41
              42  43  44  45  48  51  52  54  55  56  57
              58  60  61  62  63  65  66  67  68  69  70
              72  73  74  75  76  78  79  80  81  82  83
              84  87  88  89  91  92  93  94  95  96  97
              98  99
ISP Only: 50  47  85  49
N/C:
%%
%XC95108PQ160
XC95108PQ160 Architecture
Mnemonic: XC95108PQ160        Mnemonic: PQFP
Pin Count: 160            Total Product Terms: 99999
Extensions: D DQ AP AR CK CKMUX OE OEMUX L LQ LEMUX IOD IOL
            IOCK
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
XILINX                        XC95108(F)-(speed)PQ160C
XILINX                        XC95108(F)-(speed)PQ160I
_____________________________________________________________
Clock Pin(s): 33  35  42      Common OE(s):
VCC(s): 1  10  41  46  61  81  94  121  141  157
GND(s): 20  31  40  51  70  80  99  100  110  120  127  137
        160
Input Only:
Output Only:
Input/Output: 2  4  6  8  9  11  12  13  14  15  16  17  18
              19  21  22  23  24  25  26  27  28  29  30  33
              34  35  36  37  42  43  44  45  47  49  50  52
              54  56  57  58  59  60  62  63  64  68  69  72
              74  76  77  78  79  82  84  86  87  88  89  90
              91  92  95  96  97  98  101  102  103  104  105
              106  107  108  111  112  113  114  115  116  117
              122  123  124  126  128  129  133  134  135  138
              139  140  142  143  144  145  146  147  148  152
              153  154  155  156  158  159
ISP Only: 71  73  75  136
N/C: 3  5  7  32  38  39  48  53  55  65  66  67  83  85
     93  109  118  119  125  130  131  132  149  150  151
%%
%XC95144PQ100
XC95144PQ100 Architecture
Mnemonic: XC95144PQ100        Mnemonic: PQFP
Pin Count: 100            Total Product Terms: 99999
Extensions: D DQ AP AR CK CKMUX OE OEMUX L LQ LEMUX IOD IOL
            IOCK
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
XILINX                        XC95144(F)-(speed)PQ100C
XILINX                        XC95144(F)-(speed)PQ100I
_____________________________________________________________
Clock Pin(s): 24  25  29      Common OE(s):
VCC(s): 7  28  40  53  59  90  100
GND(s): 2  23  33  46  64  71  77  86
Input Only:
Output Only:
Input/Output: 1  3  4  5  6  8  9  10  11  12  13  14  15
              16  17  18  19  20  21  22  24  25  26  27
              29  30  31  32  34  35  36  37  38  39  41
              42  43  44  45  48  51  52  54  55  56  57
              58  60  61  62  63  65  66  67  68  69  70
              72  73  74  75  76  78  79  80  81  82  83
              84  87  88  89  91  92  93  94  95  96  97
              98  99
ISP Only: 50  47  85  49
N/C:
%%
%XC95144PQ160
XC95144PQ160 Architecture
Mnemonic: XC95144PQ160        Mnemonic: PQFP
Pin Count: 160            Total Product Terms: 99999
Extensions: D DQ AP AR CK CKMUX OE OEMUX L LQ LEMUX IOD IOL
            IOCK
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
XILINX                        XC95144(F)-(speed)PQ160C
XILINX                        XC95144(F)-(speed)PQ160I
_____________________________________________________________
Clock Pin(s): 33  35  42      Common OE(s):
VCC(s): 1  10  41  46  61  81  94  121  141  157
GND(s): 20  31  40  51  70  80  99  100  110  120  127  137
        160
Input Only:
Output Only:
Input/Output: 2  3  4  5  6  7  8  9  11  12  13  14  15  16
              17  18  19  21  22  23  24  25  26  27  28  29
              30  32  33  34  35  36  37  38  39  42  43  44
              45  47  48  49  50  52  53  54  55  56  57  58
              59  60  62  63  64  65  66  67  68  69  72  74
              76  77  78  79  82  83  84  85  86  87  88  89
              90  91  92  93  95  96  97  98  101  102  103
              104  105  106  107  108  109  111  112  113  114
              115  116  117  122  123  124  125  126  128  129
              130  131  133  134  135  138  139  140  142  143
              144  145  146  147  148  149  150  151  152  153
              154  155  156  158  159
ISP Only: 71  73  75  136
N/C:
%%
%XC95216PQ160
XC95216PQ160 Architecture
Mnemonic: XC95216PQ160        Mnemonic: PQFP
Pin Count: 160            Total Product Terms: 99999
Extensions: D DQ AP AR CK CKMUX OE OEMUX L LQ LEMUX IOD IOL
            IOCK
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
XILINX                        XC95216(F)-(speed)PQ160C
XILINX                        XC95216(F)-(speed)PQ160I
_____________________________________________________________
Clock Pin(s): 33  35  42      Common OE(s):
VCC(s): 1  10  41  46  61  81  94  121  141  157
GND(s): 20  31  40  51  70  80  99  100  110  120  127  137
        160
Input Only:
Output Only:
Input/Output: 2  3  4  5  6  7  8  9  11  12  13  14  15  16
              17  18  19  21  22  23  24  25  26  27  28  29
              30  32  33  34  35  36  37  38  39  42  43  44
              45  47  48  49  50  52  53  54  55  56  57  58
              59  60  62  63  64  65  66  67  68  69  72  74
              76  77  78  79  82  83  84  85  86  87  88  89
              90  91  92  93  95  96  97  98  101  102  103
              104  105  106  107  108  109  111  112  113  114
              115  116  117  122  123  124  125  126  128  129
              130  131  133  134  135  138  139  140  142  143
              144  145  146  147  148  149  150  151  152  153
              154  155  156  158  159
ISP Only: 71  73  75  136
N/C:
%%
%XC95216HQ208
XC95216HQ208 Architecture
Mnemonic: XC95216HQ208        Mnemonic: HQFP
Pin Count: 208            Total Product Terms: 99999
Extensions: D DQ AP AR CK CKMUX OE OEMUX L LQ LEMUX IOD IOL
            IOCK
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
XILINX                        XC95216(F)-(speed)HQ208C
XILINX                        XC95216(F)-(speed)HQ208I
_____________________________________________________________
Clock Pin(s): 44  46  55      Common OE(s):
VCC(s): 1  11  26  53  59  65  79  92  105  124  132  153
        157  172  181  184  204
GND(s): 2  13  24  27  42  52  66  68  69  81  93  104  108
        129  130  141  156  163  177  190  207
Input Only:
Output Only:
Input/Output: 3  4  5  6  7  8  9  10  12  14  15  16  17  18
              19  20  21  22  23  25  28  29  30  31  32  33
              34  35  36  37  38  39  40  41  43  44  45  46
              47  48  49  50  51  54  55  56  57  58  60  61
              62  63  64  67  70  71  72  73  74  75  76  77
              78  80  82  83  84  85  86  87  88  89  90  91
              95  97  99  100  101  102  103  106  107  109
              110  111  112  113  114  115  116  117  118  119
              120  121  123  125  126  127  128  131  133  134
              135  136  137  138  139  140  142  143  144  145
              146  147  148  149  150  151  152  154  155  158
              159  160  161  162  164  165  166  167  168  169
              170  171  173  174  175  178  179  180  182  185
              186  187  188  189  191  192  193  194  195  196
              197  198  199  200  201  202  203  205  206  208
ISP Only: 94  96  98  176
N/C:
%%
%XC95288HQ208
XC95288HQ208 Architecture
Mnemonic: XC95288HQ208        Mnemonic: HQFP
Pin Count: 208            Total Product Terms: 99999
Extensions: D DQ AP AR CK CKMUX OE OEMUX L LQ LEMUX IOD IOL
            IOCK
_____________________________________________________________
Manufacturer                  Device Name
------------                  -----------
XILINX                        XC95288(F)-(speed)HQ208C
XILINX                        XC95288(F)-(speed)HQ208I
_____________________________________________________________
Clock Pin(s): 44  46  55      Common OE(s):
VCC(s): 1  11  26  53  59  65  79  92  105  124  132  153
        157  172  181  184  204
GND(s): 2  13  24  27  42  52  66  68  69  81  93  104  108
        129  130  141  156  163  177  190  207
Input Only:
Output Only:
Input/Output: 3  4  5  6  7  8  9  10  12  14  15  16  17  18
              19  20  21  22  23  25  28  29  30  31  32  33
              34  35  36  37  38  39  40  41  43  44  45  46
              47  48  49  50  51  54  55  56  57  58  60  61
              62  63  64  67  70  71  72  73  74  75  76  77
              78  80  82  83  84  85  86  87  88  89  90  91
              95  97  99  100  101  102  103  106  107  109
              110  111  112  113  114  115  116  117  118  119
              120  121  123  125  126  127  128  131  133  134
              135  136  137  138  139  140  142  143  144  145
              146  147  148  149  150  151  152  154  155  158
              159  160  161  162  164  165  166  167  168  169
              170  171  173  174  175  178  179  180  182  185
              186  187  188  189  191  192  193  194  195  196
              197  198  199  200  201  202  203  205  206  208
ISP Only: 94  96  98  176
N/C:
%%

